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hopenaiber
Visitor
Visitor
3,110 Views
Registered: ‎10-28-2010

Black Box configuration wizard & special type of port

On simulink, I have to make a black box with an entity, but the man who has build this one has used special port types.

This types are array of std logic vector, define like this in a package file :

"type t_new_data_adc        is array (natural range <>) of std_logic_vector(C_ADC_SCALED_NB_BITS-1 downto 0);"

 

 

Because of it, the black box configuration wizard make an error and could not create a block initialization m-function.

It says me "could not parse" because ports have to be either std_logic or std_logic_vector.

 

can you help me, please?

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chrisar
Xilinx Employee
Xilinx Employee
3,081 Views
Registered: ‎08-01-2007

You will need to create a wrapper around this IP that maps the custom signals to STD_LOGIC and STD_LOGIC_VECTOR.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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talon
Observer
Observer
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Registered: ‎02-05-2019

I realise I'm asking a question to a reply to an answer from a decade ago, but in my case, it is very inefficient to wrap the file and map to custom std_logic and std_logic_vector signals. The reason for this is that a generic parameter sets the number of input ports (effectively by making use of a std_logic_vector array). I'd like to have an entity description as follows:

entity blah is
generic (
nports : natural := 4
);
port(
arrofports : in stdlogicvectorarray(nports-1 downto 0)
);
end entity blah;

and then have a config.m file for my black box that contains something like the following:

entityName = sprintf('blah');
simulink_block = this_block.blockName; 
nports = eval(get_param(simulink_block,'nports')); 
for i=0:nports-1
this_block.addSimulinkInport(sprintf('arrofports(%d)',i));
end 
this_block.addGeneric('nports','integer','nports');

A lot of the above MATLAB code is sourced from the Xilinx System Generator for DSP guide (page 388). In my case, however, rather than have 4 separate top VHDL files, I'm looking to have a single top HDL file with an array port. Given the nature of my HDL, I'd have to have 10+ top HDL files if I did it in the way they instructed.

Basically I'm looking to knit the arrofports(i) signals to drawn ports on the black box in Simulink. Would this work? Is there a different way?

Thanks.

PS. Apologies if this should've been asked as a new question, but it is in line with the original question.

Talon.

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