i have developed a model for a power converter in Simulink and generated a VHDL code using HDL coder. The output is 55 files. I verified the codes by using HDL verifier and ModelSim. The results of the cosimulation were identical to the original model. So i believe that the codes are properly generated.
Now i tried to verify the codes by Xilinx System Generator black box as shown in the figure, but the results are not the same anymore.
For the first 0.05 seconds all outputs are correct but then they are not. This means that the data types are handled correctly as well as the inputs such as clk , reset and clock_enable.
Moreover i read the help of the black box and i followed the requirements on HDL for Black Boxes.
I am really confused and i don't know why the results are not correct from the black box.
Did anyone face a similar problem or can suggest some way to troubleshoot the problem?