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Contributor
Contributor
532 Views
Registered: ‎11-08-2018

COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

Does Kintex Ultrascale have these marco for ULTRASCALE? I would like to use the DSP48E2 for these two macros if available. 

Vivado 2018.3 does not list COUNTER_TC_MACRO and COUNTER_LOAD_MACRO in  Language template. It has the template for 7 Series

 

Thanks,

A

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5 Replies
486 Views
Registered: ‎06-21-2017

Re: COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

Why not just code a counter in VHDL or verilog?  Why use a DSP48E for a simple counter?

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Contributor
Contributor
475 Views
Registered: ‎11-08-2018

Re: COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

when you use DSP block for counter you can reduced the variability in cell and net delays due to FPGA recompile.

DSP48 is kind of a hard marco and once set it would give repeatable results.

 

-A

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434 Views
Registered: ‎06-21-2017

Re: COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

You can just instantiate a DSP48E and code it to count.  It shouldn't be too hard.  I still don't see the point.  I've been doing this for 20 years and I don't think I have ever seen a design of reasonable complexity fail to make timing because of a simple counter unless the counter is very large.  What is your target clock frequency?

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Contributor
Contributor
396 Views
Registered: ‎11-08-2018

Re: COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

I tried using the DSP48E2 and I get the following warning messages during synthesis. Is there any document which provides how the unsed net for DSP48E2 needs to be connected?

 

[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port CE
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port ACLR
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port ASET
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port AINIT
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port SCLR
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port SSET
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port SINIT
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port T
[Synth 8-3331] design c_gate_bit_v12_0_5_viv has unconnected port EN
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEA1
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEA2
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEB1
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEB2
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEAD
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CED
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEC
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CECARRYIN
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CECTRL
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEALUMODE
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEINMODE
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEM
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port CEP
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRA
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRB
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRC
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRD
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRALLCARRYIN
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRCTRL
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRALUMODE
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRINMODE
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRM
[Synth 8-3331] design xbip_dsp48e1_wrapper_v3_0 has unconnected port SCLRP
[Synth 8-3331] design xbip_pipe_v3_0_5_viv__parameterized1 has unconnected port CLK
[Synth 8-3331] design xbip_pipe_v3_0_5_viv__parameterized1 has unconnected port CE
[Synth 8-3331] design xbip_pipe_v3_0_5_viv__parameterized1 has unconnected port SCLR
[Synth 8-3331] design xbip_pipe_v3_0_5_viv__parameterized1 has unconnected port SSET
[Synth 8-3331] design xbip_pipe_v3_0_5_viv__parameterized1 has unconnected port SINIT
[Synth 8-3331] design xbip_pipe_v3_0_5_viv has unconnected port CLK
[Synth 8-3331] design xbip_pipe_v3_0_5_viv has unconnected port CE
[Synth 8-3331] design xbip_pipe_v3_0_5_viv has unconnected port SCLR
[Synth 8-3331] design xbip_pipe_v3_0_5_viv has unconnected port SSET
[Synth 8-3331] design xbip_pipe_v3_0_5_viv has unconnected port SINIT
[Synth 8-3331] design dsp48_counter has unconnected port N_TC
[Synth 8-3331] design dsp48_counter has unconnected port UP
[Synth 8-3331] design xbip_counter_v3_0_5_viv has unconnected port CE
[Synth 8-3331] design xbip_counter_v3_0_5_viv has unconnected port LOAD
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port SSET
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port SINIT
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port CE
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port SSET
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port SINIT
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port UP
[Synth 8-3331] design c_counter_binary_v12_0_12_viv has unconnected port LOAD

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391 Views
Registered: ‎06-21-2017

Re: COUNTER_TC_MACRO & COUNTER_LOAD_MACRO

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