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Observer
Observer
11,542 Views
Registered: ‎10-21-2007

Could I use Modelsim and Synplify to see the result from acceldsp

I found that the files acceldsp generated in Project Explorer were partly recognized by Modelsim.If I want to see the waveforms and RTL technology of the results,could I use Modelsim and Synplify?If not,is there any methods else?Thanks!
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Xilinx Employee
Xilinx Employee
11,526 Views
Registered: ‎08-21-2007

Gusichen,
 
In the working directory there are directories (for example - VHDL\ModelsimRTL) that contain the ModelSim ".do" files so you can view the waveforms in the ModelSim GUI.  In ModelSim you could type:
 
do vcom.do
do vsim.do
do wave.do
run -all
 
There is also a Synplicity .prj project file (in the synplify_pro directory) so you can load the AccelDSP project in Synplify.
 
Let us know if you would like more information.
 
Tim
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Observer
Observer
11,520 Views
Registered: ‎10-21-2007

Thanks a lot, tim! I tried your method to watch the waveform with Modelsim,but there's no 'vcom' command.I checked the *.do files generated by acceldsp in the ModelsimRTL directory,no file named vcom.do was found while vsim.do,wave.do was found.I watched the waveform generated,but I think it's the wrong result for there was no clk signal and no ouput changing according to clk.Could you be kind to send me some examples(pdf or video),Thanks a lot!
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Observer
Observer
11,520 Views
Registered: ‎10-21-2007

Thanks a lot, tim! I tried your method to watch the waveform with Modelsim,but there's no 'vcom' command.I checked the *.do files generated by acceldsp in the ModelsimRTL directory,no file named vcom.do was found while vsim.do,wave.do was found.I watched the waveform generated,but I think it's the wrong result for there was no clk signal and no ouput changing according to clk.Could you be kind to send me some examples(pdf or video),Thanks a lot!
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Xilinx Employee
Xilinx Employee
11,507 Views
Registered: ‎08-21-2007

Hi,
 
If you are using Verilog the file is called vlog.do not vsim.do.  Also make sure your Simulation tool in AccelDSP is set to "ModelSim" and then run the simulation inside of AccelDSP one time to generate the necessary files on disk.  Then you can load a seperate ModelSim and use the .do files I mentioned.  Let us know if you have any further questions.
 
For Verilog:
do vlog.do
do vsim.do
do wave.do
run -all
 
For VHDL:
do vcom.do
do vsim.do
do wave.do
run -all
 
Best regards,
Tim
 
 
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Observer
Observer
11,503 Views
Registered: ‎10-21-2007

thanks very much,tim.I got it!Use vlog.do instead of vcom.do!
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