UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mdemirtas89
Visitor
257 Views
Registered: ‎09-02-2018

DDS Compiler Output

The DDS Compiler v6.0's Product guide (PG141) states that "3-bit to 26-bit signed output sample precision."  is possible using this core. If I choose quadrature output option, the following graph can be seen on simulation screen(which is fine): Ekran Alıntısı.JPG

My question is , if I want to give those signals to an output through a DAC (for example, in my case i use PMODDA2) and if my DAC accepts unsigned numbers as an input, how can I obtain them correctly on my oscilloscope? 

This is my oscilloscope screen : IMG_20191021_160123.jpg

 

 

 

 

0 Kudos
3 Replies
Visitor mdemirtas89
Visitor
236 Views
Registered: ‎09-02-2018

Re: DDS Compiler Output

My DDS compiler component: 

component dds_compiler_0
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);

And Its port map:

dds : dds_compiler_0 port map( aclk=>clk,m_axis_data_tvalid=>led1,
m_axis_data_tdata(31 downto 16) => temp_sin,
m_axis_data_tdata(15 downto 0) => temp_cos );

temp_sin & temp_cos signals hold values for the sinus and cosinus signals. However, they are represented in signed format. To feed my DAC's input i need unsigned format... simply converting from signed to un-signed does not work here...

0 Kudos
Highlighted
219 Views
Registered: ‎06-21-2017

Re: DDS Compiler Output

You need to map the signed value 0x8000 to 0x0000.  You need to map the signed value 0x0000 to 0x8000.  You need to map the signed value 0x7fff to the value 0xffff.  This can be accomplished by adding 0x8000 to every sample, then truncating back to 16 bits.

Visitor mdemirtas89
Visitor
179 Views
Registered: ‎09-02-2018

Re: DDS Compiler Output

Thank you Bruce... I followed your suggestion.

I mapped the temp signals' range (-2048 to 2047) to (0 to 4095) by adding 0x800 and convert them to std_logic_vector so that sin_out and cos_out signals can be fed to the DAC's data inputs... It seems to be working.

(signal) sin_out <= std_logic_vector(unsigned(temp_sin(11 downto 0)) + "100000000000" );
(signal) cos_out <= std_logic_vector(unsigned(temp_cos(11 downto 0)) + "100000000000" );