01-29-2020 09:11 AM
I'm currently building a signal generator using 2 32-bit wide phase accumulator DDS Compiler cores in parallel. I've set the 'phase increment' and 'phase offset' fields to 'programmable'. I want to generate quadrature samples from a wave with zero phase offset and a wave with a half cycle phase offset. I've generated the correct phase increment and successfully got the correct output from the first DDS with zero phase offset.
My question is what value am I meant to supply to the 'poff' for the second DDS core? As i understand there are 32-bits allocated to the phase increment and phase offset values and strung together to form a 64-bit input to the 's_axis_config_tdata' port. I've set the 'pinc' value of DDS 2 to the phase increment. and I've tried setting 'poff' value of DDS 2 to (phase increment/2) however this doesnt give the correct results. Is it the case I have to instead supply the phase offset in terms of radians (pi) or the amount of cycles I want it to be offset (0.5) and just treat the 32 bits as the fractional part of a binary number?
01-29-2020 09:48 AM
For quadrature, don't you want a 90 degree offset (quarter wave) instead of a 180 degree (half wave) offset? If so, one DDS can produce bothSINE and COSINE.
01-29-2020 11:07 AM - edited 01-29-2020 11:08 AM
I should have been more clear. My 2 DDS' are set to output quadrature signals but I want a higher sampling rate than the clock frequency (super sampling) so i want to generate 2 samples of the quadrature signals on every rising edge of the system clock (4 samples in total). The first pair of samples of the clock cycle will be a zero phase offset sin and cos samples and the second pair will be a half cycle phase offset sin and cos sample.
04-28-2021 01:48 AM
I try to achieve the same thing (phase increment/2). I want the output from a DDS_2 at the same frequency than a DDS_1 but with half sample offset
I am working with the DDS compiler MATLAB model. Everything that I tried results in a 1 sample offset at most. Did you get any success since you posted ?
04-28-2021 11:36 PM
For super sample rate DDS, please refer to the Vector DDFS block in System Generator. The DDS Compiler IP does not support super sample rate.