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Observer pau-bergada
Observer
982 Views
Registered: ‎07-07-2017

DDS compiler not configured

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Dear member forums,

I am struggling to reconfigure a DDS IP core to a given frequency through its CONFIG port.

The fact is that the simulation works fine but when I download the code and configure my XC7S25 it does not accept reconfigurations of PHASE_INC to change the DDS frequency and consequently it always runs at the initial frequency (programed by means of the GUI).  

 

The circuit works with a 12.288 MHz clock, the DDS is configured to output 3 channels with a sampling frequency of 4.096 Msps each. The phase width is 32 bits. Phase Increment and Offset Programmability are both set to Programmable. 

As you can see in the attached figures, the one related to the simulation process of the IP core shows an expected behavior: it is first configured with an increment of phase to generate a 200 kHz tone and then reconfigured to generate a 400 kHz tone. Everything nice.

However, the picture related to the debugging process inside the XC7S25 shows a failure to reconfigure the frequency and hence always runs at the initial frequency (100 kHz).

 

I will appreciate any comment that can shed some light on this issue.

Thank you so much.            

 

 

Tags (2)
DDS_simulated_200kHz_400kHz.JPG
DDS_imlemented_S7.JPG
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1 Solution

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Observer pau-bergada
Observer
855 Views
Registered: ‎07-07-2017

Re: DDS compiler not configured

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Ily,

I've just discovered the source of my problem. It was related to a bad connection in the block diagram. When debugging the CONFIG interface of the DDS compiler IP, as well as all other IPs, by means of an ILA core I used a Native Monitor Type instead of an AXI Monitor Type and that's the source of my problem. What it happened is that while succesfuly monitoring these signals on the AXI master, the AXI slave (in this case the DDS_compiler) remained disconnected.

 

What gave me a clue is this warning: 

[BD 41-1271] The connection to the pin: /TEST_DDS_0/m_axis_data_tvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: TEST_DDS_0_m_data

 

So be careful when debugging an interface connection with a Native Monitor Type because VIVADO disconnects the pin as a part of the interface connection and you must manualy connect it to the slave.

 

Thank you for your time.

     

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6 Replies
Observer pau-bergada
Observer
941 Views
Registered: ‎07-07-2017

Re: DDS compiler not configured

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I have just check the device family list that supports DDS IP core and unfortunately, Spartan-7 does not appear on it. Is it related to the problem I have just come across?

 

Thank you.

 

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Xilinx Employee
Xilinx Employee
903 Views
Registered: ‎08-02-2007

Re: DDS compiler not configured

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have you checked if any errors are seen when config interface is working

any information of event_s_config_tlast_missing or event_s_config_tlast_unexpected ?

 

The DDS should have been only tested in the listed devices

but since it is a softcore, Spartan 7 should work fine too

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Observer pau-bergada
Observer
890 Views
Registered: ‎07-07-2017

Re: DDS compiler not configured

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ily,

thank you for your reply.

 

I have never seen any pulse on any of these signals (CONFIG_tlast_missing and CONFIG_tlast_unexpected).

However, I have tried to check if these signals were alive and I have togled the TLAST signal on CONFIG port during a reconfiguration period (TVALID high during 12 periods:12 channels) to check if tlast_unexpected signal would be asserted and to my surprise it never goes high, as you can see on the attached plot. Then what I guess is that the CONFIG port of DDS is not active and does not see any configuration request at any time. 

However, the DDS core still works as initially configured without any issue.

 

Would you please give some clue where to target my efforts?

Thank you so much.

 

 

 

 

   

 

DDS_imlemented_S7_4.JPG
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Xilinx Employee
Xilinx Employee
872 Views
Registered: ‎08-02-2007

Re: DDS compiler not configured

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during tvalid is asserted , I noticed that tlast was asserted twice

could you please try to change that

the tlast should only asserted when the last channel config is fininshed

 

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Observer pau-bergada
Observer
863 Views
Registered: ‎07-07-2017

Re: DDS compiler not configured

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Ily,

thank you for your comments.

The double TLAST assertion during a TVALID cycle was made on purpose to check whether the DDS core acknowledge a configuration process. The point is that the DDS core does not issue a pulse on TLAST_UNEXPECTED output, as it would be expected. I've already tried with asserting TLAST only once the last channel configuration is finished; with no success. Moreover, opposite to what simulation shows on the first plot, TREADY does not go low during a TVALID process.

 

So it seems there's a problem with IP cores that do not acknowledge any configuration process. I've just check that this issue also repeats with other IP cores in the project, such as CIC compiler and FIR compiler. Hence it seems a general case affecting all IPs in my project, which can be related to the FPGA used (XC7S25) or to some error building the project. The fact is that I haven't seen any error or critical warning during Synthesis or Implementation process related to this issue.

 

I would appreciate any idea that can help me move fordward.

Thank you so much.           

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Observer pau-bergada
Observer
856 Views
Registered: ‎07-07-2017

Re: DDS compiler not configured

Jump to solution

Ily,

I've just discovered the source of my problem. It was related to a bad connection in the block diagram. When debugging the CONFIG interface of the DDS compiler IP, as well as all other IPs, by means of an ILA core I used a Native Monitor Type instead of an AXI Monitor Type and that's the source of my problem. What it happened is that while succesfuly monitoring these signals on the AXI master, the AXI slave (in this case the DDS_compiler) remained disconnected.

 

What gave me a clue is this warning: 

[BD 41-1271] The connection to the pin: /TEST_DDS_0/m_axis_data_tvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: TEST_DDS_0_m_data

 

So be careful when debugging an interface connection with a Native Monitor Type because VIVADO disconnects the pin as a part of the interface connection and you must manualy connect it to the slave.

 

Thank you for your time.

     

0 Kudos