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Contributor
Contributor
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Registered: ‎08-28-2020

DSP48E2 instantiation for multiplication

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I'm trying to instantiate DSP48E2 of zynq ultrascale for multiplication operation but it returns P output zero always even if the control signals were properly given. (shown in following instantiation code)
 
module top(CLK, A, B, C, ACOUT, BCOUT, P);
input wire CLK;
input wire signed [29:0] A;
input wire signed [17:0] B;
input wire signed [47:0] C;
output wire signed [29:0] ACOUT;
output wire signed [17:0] BCOUT;
output wire signed [47:0] P;
DSP48E2#(
.AMULTSEL("A"),
.A_INPUT("DIRECT"),
.BMULTSEL("B"),
.USE_MULT("MULTIPLY")
)
DSP48E2_inst (
.ACOUT(ACOUT),
.BCOUT(BCOUT),
.P(P),
.ALUMODE(4'd0),
.CARRYINSEL(3'd0),
.CLK(CLK),
.INMODE(5'd0),
.OPMODE(9'd5),
.A(A),
.B(B),
.C(C),
.CARRYIN(1'd0),
.CEA2(1),
.CEALUMODE(1),
.CEB2(1),
.CEC(1),
.CEINMODE(1),
.CEM(1),
.CEP(1),
.RSTA(0),
.RSTALUMODE(0),
.RSTB(0),
.RSTC(0),
.RSTCTRL(0),
.RSTM(0),
.RSTP(0)
);
endmodule
In this module, ACOUT and BCOUT are connected to verify their functionality and those 2 are working properly as given in the following simulation waveform. Can anyone tell me what went wrong with P output. (which needs to return the multiplication output of A and B)
 
ACOUT and BCOUT signal behaviour.PNG
 
Inference and DSP48 macro usage can be done for this. In order to utilize the complete flexibility over DSP48E2, I want to do the instantiation. So this question is only about instantiation.
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Contributor
Contributor
367 Views
Registered: ‎08-28-2020

I already mentioned this only consider the use of instantiation.

By activating CECTRL clock enable signal to OPMODEREG and CARRYINSEL, partial products of multiplication output can be obtained through X and Y multiplexers and it can be added with C input (coming from port or CREG) as given in following simulation waveform. (Here fabric registers hasn't been used to pipeline the C input for addition with partial products of multiplication output)

multiplication with post addition with CREG being one.PNG

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

Have you tried using the DSP48 Macro LogiCORE IP (PG148; v3.0)?

forums_dsp48macro_1.png

forums_dsp48macro_2.pngforums_dsp48macro_3.png

 

Highlighted
Contributor
Contributor
368 Views
Registered: ‎08-28-2020

I already mentioned this only consider the use of instantiation.

By activating CECTRL clock enable signal to OPMODEREG and CARRYINSEL, partial products of multiplication output can be obtained through X and Y multiplexers and it can be added with C input (coming from port or CREG) as given in following simulation waveform. (Here fabric registers hasn't been used to pipeline the C input for addition with partial products of multiplication output)

multiplication with post addition with CREG being one.PNG

 

View solution in original post

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