02-26-2013 03:07 AM
I'm trying to make a simple design in sysgen for, I only want to run a counter and get the result by leds.
I used to program VIRTEX 5 in vhdl and I always convert the differential clock input in a signal to work with, this time I can't find the way to configure a differential clock input in sysgen.
02-26-2013 03:18 AM
You need to instantinate a clock buffer, which converts differential signal to single-ended. I usually do it by managing project in ISE and instantinating SysGen design as a module, and clock buffer as the module too. Then I connect CLK lines of sysgen design in VHDL Top Module.
02-28-2013 07:42 AM
I know how to get a single-ended clk but I don't know how to connect the single end clk to the clk of the sysgen design.
02-28-2013 07:58 AM
I don't know how to connect the single end clk to the clk of the sysgen design.
You have to learn ISE a little bit. When you generate VHDL from Sysgen design then CLK port appears as input to your module.
03-01-2013 12:53 AM
I know that, but the problem is that if I add only the 2 VHDL files which are generated by sysgen, is not working I have errors about clk_(and a lot of numbers). If I open as a project is also possible to change it?
03-01-2013 02:56 AM
You have to create a Top level VHDL Module, where you instantinate Sysgen and Clock buffer modules, using ther instatntination templates. Then you connect CLK lines using signals and generate constraints files.
ISE has functionality to include whole Sysgen - e.g you can open it from ISE in MATLAB.
04-22-2013 10:11 PM