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norbertreifschneider
Contributor
Contributor
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Registered: ‎01-28-2018

Divider Generator Problem

Hi all,

I have some severe problems with a divider created by Divider Generator (5.1) in VIVADO.

First of all, I want to have a remainder divider 28 bit by 24 bit.

On the first image attached, you see, if I enter a dividend width of 28, this is not accepted and the systems shows a bit ordering of 31 .. 0 on the left side. I have to create a component declaration in the later design with a dividend width of 32 instead of 28 (second image attached).

The next problem is true for simulation and implementation.

Within the design, the final divider is connected as shown in the 3. image attached.

The inputs "DividendValid" and "DivisorValid" are connected to the same driver signal marked in the 4. image attached.

The signal becomes high for 1 clock period at a certain time, but the divider never responds with a 1 at the "DoutValid" output. This is true for the simulation and for the implemented design (controlling FSM stucks when waiting for the "DoutValid").

I also tried to connect the "DividendValid" to a constant 1, but this works neither.

The funny thing is, within a test design where only 2 dividers are present, this works!

What may be the reason for this misbehaviour?

NOrbert

 

DIV_Shit4.jpg
DIV_Shit3.jpg
DIV_Shit2.jpg
DIV_Shit1.jpg
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norbertreifschneider
Contributor
Contributor
434 Views
Registered: ‎01-28-2018

A reminder:

I use the block design because the direct generation of the divider via IP Catalog fails with the error meesage:

INFO: [VRFC 10-163] Analyzing VHDL file "XXX.srcs/sources_1/ip/DIV_28_24_1/demo_tb/tb_DIV_28_24_1.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_DIV_28_24_1'
ERROR: [VRFC 10-2987] 'div_28_24_1' is not compiled in library 'xil_defaultlib' [XXX/VCU108_1/ETHMiner.srcs/sources_1/ip/DIV_28_24_1/demo_tb/tb_DIV_28_24_1.vhd:179]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [XXX/VCU108_1/ETHMiner.srcs/sources_1/ip/DIV_28_24_1/demo_tb/tb_DIV_28_24_1.vhd:77]
INFO: [VRFC 10-3070] VHDL file 'XXX/VCU108_1/ETHMiner.srcs/sources_1/ip/DIV_28_24_1/demo_tb/tb_DIV_28_24_1.vhd' ignored due to errors
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:39 . Memory (MB): peak = 8365.590 ; gain = 0.000

 

Is there still no fix available for this bug??

Norbert

 

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