Error: An error occurred when creating the Vivado project... Block: Unspecified

[namrata_kogalur]

I am taking the sysgen tutorials and following ug948-vivado-sysgen-tutorial.pdf . I am not able to generate to compile the design into hardware.    

 

Summary of Errors:
Error 0001: ERROR: An error occurred when creating the Vivado project...
Block: Unspecified
--------------------------------------------------------------------------------

Error 0001:

Reported by:
Unspecified

Details:
ERROR: An error occurred when creating the Vivado project.
error copying "{C:/Users/Namrata
Kogalur/Desktop/mitacs/project/ug948-design-files/SysGen_Tutorial/Lab1/netlist/sysgen/lab1_1_clock.xdc}":
no such file or directory
INFO: [Common 17-206] Exiting Vivado at Fri Jun 10 11:28:07 2016..

I have attached my model.

[balkris]

are you getting this error with all the designs are specific to current design . This can be installation issue is all designs failing with same error

[adityadhananjay]

Hello Namrata,

I had the same problem. The issue is this: In your file path, there is a space in "Namrata Kogalur". Xilinx does not like path/file names with spaces. Move the project to a different directory without spaces in the name. Your design will then be able to find the correct XDC file. Good luck!

Aditya

[kshitijgoel]

Error has been resolved by deselecting the option "Post-synthesis" in the system generator token in the compilation tab.

[amir20am]

Hi
i couldnt find post-synthesis in my system generator token in the compilation tab.
can you show it by sending an image?
thanks