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Visitor
Visitor
5,806 Views
Registered: ‎07-04-2011

Error synthesizing RAM

Hi everyone,

 

I've created a Design with System Generator containing a Block RAM. I'm using ISE 13.1 and Matlab R2009a.

If I try to synthesize the model, I get the following error:

 

ERROR:Xst:2585 - Port <ena> of instance <comp0.core_instance0> does not exist in definition <bmg_52_ee25581af35c1622>. Please compare the definition of block <bmg_52_ee25581af35c1622> to its component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <enb> of instance <comp0.core_instance0> does not exist in definition <bmg_52_ee25581af35c1622>. Please compare the definition of block <bmg_52_ee25581af35c1622> to its component declaration to detect the mismatch.
entity <bmg_52_ee25581af35c1622> with generics:
  box_type: from attribute on component : no-type := "black_box"
  fpga_dont_touch: from attribute on component : no-type := "true"
  syn_black_box: from attribute on component : no-type := true

 

The error occurs either if I use the dual port RAM or the single port RAM.

 

Does anybody know the reason for this error and how to solve or work around it?

 

Thanks for any help,

 

Hennes

 

 

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7 Replies
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Xilinx Employee
Xilinx Employee
5,782 Views
Registered: ‎11-28-2007

At the risk of pointing out the obvious, Matlab R2009a is not one of Matlab versions that SysGen 13.1 supports. Check the AR below for additional info:

 

http://www.xilinx.com/support/answers/17966.htm


@herr.matzka wrote:

Hi everyone,

 

I've created a Design with System Generator containing a Block RAM. I'm using ISE 13.1 and Matlab R2009a.

If I try to synthesize the model, I get the following error:

 

ERROR:Xst:2585 - Port <ena> of instance <comp0.core_instance0> does not exist in definition <bmg_52_ee25581af35c1622>. Please compare the definition of block <bmg_52_ee25581af35c1622> to its component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <enb> of instance <comp0.core_instance0> does not exist in definition <bmg_52_ee25581af35c1622>. Please compare the definition of block <bmg_52_ee25581af35c1622> to its component declaration to detect the mismatch.
entity <bmg_52_ee25581af35c1622> with generics:
  box_type: from attribute on component : no-type := "black_box"
  fpga_dont_touch: from attribute on component : no-type := "true"
  syn_black_box: from attribute on component : no-type := true

 

The error occurs either if I use the dual port RAM or the single port RAM.

 

Does anybody know the reason for this error and how to solve or work around it?

 

Thanks for any help,

 

Hennes

 

 




Cheers,
Jim
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Highlighted
Visitor
Visitor
5,766 Views
Registered: ‎12-08-2007

I am receiving the same error using Matlab 2010b and ISE13.2.

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Highlighted
Visitor
Visitor
5,762 Views
Registered: ‎12-08-2007

Just ran a test. This issue only pops up when synthesizing for a Spartan 6 device. The Virtex6 series will synth a single port RAM just fine. If anyone has a solution other than hand fix of the HDL netlist I would be most grateful.

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Adventurer
Adventurer
5,753 Views
Registered: ‎11-12-2010

We have this same error when upgrading a desing from SysGen 13.1 and Matlab R2009b to SysGen13.2 and Matlab R2010b. This error occur only with Spartan-6 devices. Using Virtex-6 devices compiles is good.

In SysGen 13.1 requirement do not talk about R2009b Matlab version, but SysGen setup program mark R2009 as compatible.

Any solution?

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Xilinx Employee
Xilinx Employee
5,746 Views
Registered: ‎08-02-2011

It looks like error is from the enable port(s) on the BRAM.

 

Double check your settings in SysGen and compare it to your HDL ports

www.xilinx.com
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Highlighted
Adventurer
Adventurer
5,738 Views
Registered: ‎11-12-2010

The issue is about an incorrect code generation of SysGen with Spantan-6 memory.

 

I have opened a WebCase about it and Xilinx is resolving this bug. Next the temporary solution provided in the WebCase opened about this error:

 

This is a recently discovered known issue and a CR has been filed against it. The workaround is to create the HDL Netlist in Sysgen and then modify the HDL to remove the ena and enb ports from the VHDL files.
Then run the remaining design through project navigator to implement the design. This was used to workaround the problem in a previous customers design.

Alternatively, I think you can create the Dual Port RAM through Coregen and incorporate the Coregen core as a black box in your Sysgen design. Note: I have not verified this.

3rd option would be to remain with 13.1 as the issue is new to 13.2.

 

I can confirm that the BlackBox - Coregen solution works fine.

Using "Black Box Tutorial Example 2" it's easy to incorporate a core or VHDL code to SysGen, and can be simulated also.

I hope this information it will be useful.

 

Best Regards

Highlighted
5,704 Views
Registered: ‎09-28-2011

i'm having the same problem with a Virtex 6. Actually a ported the design from an older version of Sysgen and Matlab. Is that just a "porting" problem? should i have to manually add the ena ports?

Andrea Campera
CEO and Founder
Campera, The DSP Company, www.camperadsp.com
Headquarter: Via Pellettier 57, 57122, Livorno (LI), Italy
Tel: +39-329-4677083, Fax: +39-0586-076557
email: a.campera@camperadsp.com
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