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Visitor jhk
Visitor
1,037 Views
Registered: ‎05-26-2015

FFT IP-Core output order does not match with simulation

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Hi,

my problem is as follows:

I have a FFT-IP-Core with the following key-settings:
 * Transform length 16
 * pipelined Streaming I/O
 * fixed point
 * reversed Ordering
 * realtime
 
The IP-Core works as expected in simulation: generated with Vivado 2014.4 for a XC7VX485T and generated with Vivado 2017.3 for a XCKU115.
The FFT-IP-Core running in a design on the XC7VX485T delivers the expected results. However, the FFT-IP-Core running in a design on the XCKU115 delivers not the expected results (observed with an ILA-Core). My observation is as follows:

I expect the results in the following (bitreversed) order:
0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15

The tuser signal of the FFT-IP-Core delivers the expected order, but the data does not match:
The first and the second value are correct. The third and the fourth value are swapped. The 5. value deliverd by the FFT-IP-Core should be the 8. value. The 6. value matches with the 7. The 7. with the 6. ... The last value (on the FPGA) matches with the 9. of the simulation.

I use some other FFT-IP-Core instances in my design with other transform lengths, etc. (all with reversed ordering) without problems.

Is it possible, that there is a problem with this IP-Core-Settings and the XCKU115?

Thanks and Regards
Jan

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Visitor jhk
Visitor
1,327 Views
Registered: ‎05-26-2015

Re: FFT IP-Core output order does not match with simulation

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Hi @balkris,

 

thank you for the reply. 

 

The fwd_inv flag of the scaling schedule was in simulation and the design was not the same, causing a incorrect data order.

View solution in original post

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Xilinx Employee
Xilinx Employee
1,003 Views
Registered: ‎08-01-2008

Re: FFT IP-Core output order does not match with simulation

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The reason for difference may be because you may not driving the all the input correctly. Please make sure all the input driven correctly. You may dump all your control signal and see everything working fine . You may try post simulations. I am assuming you are meeting timings . You may try running the FFT design at lower frequency
Thanks and Regards
Balkrishan
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Visitor jhk
Visitor
1,328 Views
Registered: ‎05-26-2015

Re: FFT IP-Core output order does not match with simulation

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Hi @balkris,

 

thank you for the reply. 

 

The fwd_inv flag of the scaling schedule was in simulation and the design was not the same, causing a incorrect data order.

View solution in original post

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