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LAZIBI
Observer
Observer
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Registered: ‎05-12-2021

FIR Compiler 7.2 / Reloadable coefficients / Config synchronization!!

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I am working in this fir compiler for long time but until now I can't make it work with the reloadable coefficients.

I am using vitis 2020.2 for creating a fir filter. I have 3 cpp kernels that linked with an RTL kernel that has the fir compiler IP packaged as xo file from vivado202.2.

I separate the reload coeff operation in a cpp kernel  that read coeffs from Gmem and stream them to the fir compiler and in the same kernel I stream some data in the config channel to the fir compiler. 

The other 2 kernels are for stream in the input data and stream out the outputs for and from the fir compiler and they start after the reload coeffs kernel.

My output data are the same for different reloaded coeffs, so seems the reload coeffs operation doesn't work . 

I wasted a lot of time trying to understand how it works but I failed. I found out that dealing with this fir compiler using vitis it's a bit complicated. Screenshot from 2021-07-07 16-12-54.pngScreenshot from 2021-07-07 16-20-08.png  

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vkanchan
Xilinx Employee
Xilinx Employee
278 Views
Registered: ‎09-18-2018

Hi @LAZIBI ,

In addition to Nathan's steps, can you also point the number of coefficients loaded into the FIR. The FIR is configured with 768 coefficient. The reload coefficients should have the same  property and the same number of coefficients as originally configured. If the reload coefficients are less in number, append them with zeros at the end to make it of same length.

The coefficients should be same as that shown in the reload index order shown in the GUI.

 

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nathanx
Moderator
Moderator
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Registered: ‎08-01-2007

can you please capture all the direct reload channel inputs of FIR Compiler v7.2 IP? NOTE the config channel of FIR Compiler IP is blocking to the RELOAD channel. When all the reload slots are full the RELOAD channel is blocked until a configuration packet is received and processed. That means you need to send a configuration packet input to the IP after all the reloaded coefs are put into the core.

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vkanchan
Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎09-18-2018

Hi @LAZIBI ,

In addition to Nathan's steps, can you also point the number of coefficients loaded into the FIR. The FIR is configured with 768 coefficient. The reload coefficients should have the same  property and the same number of coefficients as originally configured. If the reload coefficients are less in number, append them with zeros at the end to make it of same length.

The coefficients should be same as that shown in the reload index order shown in the GUI.

 

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LAZIBI
Observer
Observer
275 Views
Registered: ‎05-12-2021

Hi @nathanx , What do you mean exactly with capture all the direct reload channel inputs of FIR Compiler?

I tried to send a config packet from the same kernel for reloaded coefs and here my code of the reload coefs cpp kernel.

 

 

#define COE_DWIDTH 32

typedef ap_axis<COE_DWIDTH, 0, 0, 0> axis;


static void stream_coeff ( ap_int<COE_DWIDTH>	*input,
		   	   	   	unsigned int num,
					hls::stream<axis> &stream,
					volatile ap_uint<8> *config
){

	 axis v ;
	  ap_uint<8> tmp_config = 0;
	  int val =0


coeff_mover:	for (unsigned int i = 0; i < num; i++) {

	 v.data = ( input[i]);

	    // assert last when last piece of data
	    v.last = (i == (num -1)) ? 1 : 0;
	    val = (i == (num -1)) ? 1 : 0;

	    // Write to stream interface
	    	stream.write(v);
	  	  if(val){  
tmp_config = val;	 
config.write(tmp_config) ;   }

	  }
}

extern "C" {
void reload(ap_int<COE_DWIDTH>	*coe,
		   unsigned int tab_num,
		   hls::stream<axis> &coe_stream,
		   volatile ap_uint<8> *config_r
               ) {

#pragma HLS INTERFACE m_axi port=coe offset=slave bundle=gmem_coe
#pragma HLS INTERFACE axis port=coe_stream
#pragma HLS INTERFACE axis port=config_r

stream_coeff(coe,tab_num,coe_stream,config_r);

}
}

 

 

  and you can see here the emulation and that TVALID of the config channel goes high 1 cycle when the last coef  received.

Screenshot from 2021-07-08 09-55-47.png

and my block design. Screenshot from 2021-07-08 09-53-23.png

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