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218 Views
Registered: ‎06-21-2017

FIR Compiler aresetn

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I just want to clarify what the FIR Compiler (V7.2) Product Guide says about aresetn.  "The aresetn port is an optional active-Low input port which, when asserted for a minimum of two cycles, forces the internal control logic to the initialized condition."

I have a filter with multiple reloadable coefficient sets.  The PG does not say that aresetn clears the coefficients.  Is this true?  However, it should clear the reload coefficient counter such that if I get a reload_tlast_unexpected or reload_tlast_missing error, I can clear the reload function and start cleanly.  True again?

 

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Registered: ‎08-16-2018

Re: FIR Compiler aresetn

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Hi 

When we use the reload channel, no coefficient data is reset, only the control logic is reset.

Therefore if you have provided a synchronisation event, those coefficients should still be loaded into the taps; the reset won't clear them. 

There's no way to reset the core back to using the initial coefficients, you'd need to reload those coefficients back into the core. 

 

 

 

If the core is reset following a tlast_missing event on the RELOAD channel, it is assumed that the core received a complete coefficient set and the reset does not clear the loaded coefficient vector. If only one reload slot has been specified, then a synchronisation event needs to occur before another coefficient sset can be loaded. This is reflected in the tready deassertion. If more than one reload slot has been specified, then it is possible to overwrite the previously loaded set before applying a snychronisation event

If the core is reset following a tlast_unexpected event on the RELOAD channel, it is safe to load a new complete coefficient vector before triggering a synchronization event. The new coefficient vector will overwrite the previous partial coefficient vector

So, basically, as long as the core hasn't got a complete coefficient set, you can reset the core and the reload counter will reset, and you can start a new coefficient set from scratch. 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

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Moderator
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Registered: ‎08-16-2018

Re: FIR Compiler aresetn

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Hi 

When we use the reload channel, no coefficient data is reset, only the control logic is reset.

Therefore if you have provided a synchronisation event, those coefficients should still be loaded into the taps; the reset won't clear them. 

There's no way to reset the core back to using the initial coefficients, you'd need to reload those coefficients back into the core. 

 

 

 

If the core is reset following a tlast_missing event on the RELOAD channel, it is assumed that the core received a complete coefficient set and the reset does not clear the loaded coefficient vector. If only one reload slot has been specified, then a synchronisation event needs to occur before another coefficient sset can be loaded. This is reflected in the tready deassertion. If more than one reload slot has been specified, then it is possible to overwrite the previously loaded set before applying a snychronisation event

If the core is reset following a tlast_unexpected event on the RELOAD channel, it is safe to load a new complete coefficient vector before triggering a synchronization event. The new coefficient vector will overwrite the previous partial coefficient vector

So, basically, as long as the core hasn't got a complete coefficient set, you can reset the core and the reload counter will reset, and you can start a new coefficient set from scratch. 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

View solution in original post

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