UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
680 Views
Registered: ‎07-24-2018

FIR Compiler fails place_design

Jump to solution

Currently trying to implement 16 512-tap Decimate by 4 FIR filters in Vivado for a ZU9EG device.

Running Vivado 2018.2 on Ubuntu.

Running into errors during place_design without any real explanation. The log shows:

Phase 2.1 Floorplanning
Abnormal program termination (11)
Please check '/home/[user]/Xilinx/Projects/[proj]/[proj].runs/impl_1/hs_err_pid1027.log' for details

hs_err_pid1027.log shows:

#
# An unexpected error has occurred (11)
#
Stack:
/lib/x86_64-linux-gnu/libc.so.6(+0x354b0) [0x7f9ddfec54b0]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFVPPlacer::~HAPLFVPPlacer()+0x290) [0x7f9db485e5f0]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::doVPPlacer(HAPLFVPPlacerParams const&, int&)+0x26e) [0x7f9db5225b9e]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::doVPPlacer(HAPLFVPPlacerParams const&)+0x23) [0x7f9db52378b3]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::doAltWeightsHMPlacerIterations(int, bool&, HAPLFTDMUtils::partitionWeights const&)+0x937) [0x7f9db5235e57]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::doHMPlacerIterations(int, bool&)+0x120) [0x7f9db5237170]
/home/[user]/Xilinx/Vivado/2019.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::doFloorplanning()+0x242) [0x7f9db52390e2]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::runMain1(bool&, bool&, bool, bool)+0x174) [0x7f9db52392f4]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_place.so(HAPLFQPILRPlacer::run(bool, bool, bool, bool, bool)+0x33) [0x7f9db523a463]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_implflow.so(HAPLFFastPlace3::doQPILRPlacement(unsigned int const&, bool, bool)+0x760) [0x7f9dba10a100]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_implflow.so(HAPLFFastPlace3::doGlobalPlacement(bool, bool)+0x655) [0x7f9dba10b725]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_implflow.so(HAPLFFastPlace3::doPlacement(bool, bool, unsigned int)+0xe4) [0x7f9dba10c0f4]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_implflow.so(HAPLFFastPlace3::place(HAPLPlaceApi&, HFLFloorplan&, HAPLFFastFlowParam const&, HDPLTask&, HAPLFMigPblockInfo const*)+0x7d5) [0x7f9dba10d235]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_implflow.so(HAPLFFastFlow3::place(HAPLFFastFlowParam const&, HAPLFMigPblockInfo const*)+0xd20) [0x7f9dba0d12f0]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_vivadotasks.so(+0x3e0710) [0x7f9da2eae710]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_vivadotasks.so(+0x3e4aca) [0x7f9da2eb2aca]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_common.so(+0x78e792) [0x7f9de1189792]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7f9ddb5014af]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x76875) [0x7f9ddb544875]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x7e029) [0x7f9ddb54c029]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x76) [0x7f9ddb503156]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_commontasks.so(+0x1b26b4) [0x7f9dd5e226b4]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7f9ddb5014af]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x34b38) [0x7f9ddb502b38]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0xad486) [0x7f9ddb57b486]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x346c5) [0x7f9ddb5026c5]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalEx+0x13) [0x7f9ddb5030a3]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(Tcl_FSEvalFileEx+0x1da) [0x7f9ddb567c5a]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_commontasks.so(+0x1cf84d) [0x7f9dd5e3f84d]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_common.so(+0x78e792) [0x7f9de1189792]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7f9ddb5014af]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f9ddb5015e2]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f9ddb503402]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_commontasks.so(+0x200e8f) [0x7f9dd5e70e8f]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_commontasks.so(+0x20255e) [0x7f9dd5e7255e]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_common.so(+0x78e792) [0x7f9de1189792]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7f9ddb5014af]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f9ddb5015e2]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f9ddb503402]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_commonmain.so(+0x7414) [0x7f9de07f7414]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/libtcl8.5.so(Tcl_Main+0x1d0) [0x7f9ddb56e210]
/home/[user]/Xilinx/Vivado/2018.2/lib/lnx64.o/librdi_common.so(+0x7d175b) [0x7f9de11cc75b]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x76ba) [0x7f9ddfc7a6ba]
/lib/x87_64-linux-gnu/libc.so.6(clone+0x6d) [0x7f9ddff9741d]

Any ideas on why this is happening? Resource utilization?

0 Kudos
1 Solution

Accepted Solutions
Contributor
Contributor
561 Views
Registered: ‎07-24-2018

Re: FIR Compiler fails place_design

Jump to solution

Resolved: You'll have to explicitly divide up your DSP slice columns into a custom configuration. In my case, dividing 128 slices into 4 columns of 32 worked. The synthesis tools, even under "Automatic" multi-column support mode, will not divide up your slices such that they will all fit consecutively.

View solution in original post

0 Kudos
3 Replies
Contributor
Contributor
658 Views
Registered: ‎07-24-2018

Re: FIR Compiler fails place_design

Jump to solution

Looks to be something related to # of FIR filters placed. Implemented successfully using only 8. Will try 12 and see where the boundary for success is.

0 Kudos
Contributor
Contributor
588 Views
Registered: ‎07-24-2018

Re: FIR Compiler fails place_design

Jump to solution

I've upgraded to Vivado 2018.3 and got a more helpful report. The placer can't place down 5 of the filters, although I should be well under utilization. I suspect it has something to do with lack of consecutive DSP slices.

0 Kudos
Contributor
Contributor
562 Views
Registered: ‎07-24-2018

Re: FIR Compiler fails place_design

Jump to solution

Resolved: You'll have to explicitly divide up your DSP slice columns into a custom configuration. In my case, dividing 128 slices into 4 columns of 32 worked. The synthesis tools, even under "Automatic" multi-column support mode, will not divide up your slices such that they will all fit consecutively.

View solution in original post

0 Kudos