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Hago231
Newbie
Newbie
379 Views
Registered: ‎04-23-2020

FIR Compiler s_axi_tdata_tready

Hi all,

I'm having a difficult time trying to figure out what I'm doing wrong here:

I've created an FIR Compiler v7.2 ip with reloadable coefficients. the coeffs width is 2 bits, and there is only one set and one channel.

The problem is, no matter what I do, the s_axi_tdata_tready does not change from its initial state of 'U'. I'm reloading the coeffs using the RELOAD port; upon done reloading, I'm waiting long enough until the CONFIG tvalid is triggered. Why is the s_axi_tdata_tready not changing? 

I was not sure what the s_axis_config_tdata signal should contain, since I have 1 channel and 1 coeffs set (it is 8 bits wide) - so I set it all 1s, all 0s, 01, 10 etc. Didn't matter. 

Thanks, 

Hago 

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vkanchan
Xilinx Employee
Xilinx Employee
289 Views
Registered: ‎09-18-2018

Hi @Hago231 ,

Did you try simulating the FIR IP with its example test bench ? If not, could you check if the IP shows the same behavior with the example test bench ?

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