FIR Compiler v4.0 works in SysGen simulation, coefficients seems to be all zero in hardware

[jpnaude]

Hi

We've run into a problem where we get all zeros out of our filter in hardware. RDY behaves as expected, thus it seems like the coefficients (mif) file is not loaded during implementation or something else causes the coefficients to be all zeros in hardware. 

How can we check if this is the case? Or what else can cause the filter to produce only zeros.

Its a SysGen design compiler into a .ngc, instantiated in a bigger design.

Thanks,

Jaco

[criley]

Hi Jaco,

If this is a Virtex-5 design and you are using 10.1 SP1 or older software it may be related to a known issue where INIT values get set to all zero when MAP packs RAM18's with a FIFO in a RAMB36 Component.

Answer Record 30600 hits on this issue:

http://www.xilinx.com/support/answers/30600.htm

If you can't upgrade your software then you'll need to generate the HDL or NGC Netlist in SysGen, then open the project in ISE and manually lock the BRAM and FIFO instances to different sites or use a packing constraint to prevent this from occurring.

-Chris 

[jpnaude]

Hi Chris

Thanks for the reply. Unfortunately (fortunately maybe) we are using version 11.1 of all the tools so it should not be the problem, unless its a regression or something. 

Can you please shed some more light on how the coefficients are loaded into the core (or any other netlist for that matter)? We see two files, a MIF file and a COE file. As far as I know the MIF file is for simulation, and the COE file is used by XST to create the netlist. 

Thus, are the init values embedded into the netlist? Or at which stage are they supposed to be merged?

Thanks again,

Jaco

[ywu]

The coeffiicients are embedded into the ngc netlist during synthesis (xst).