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Newbie tianzhi4981
Newbie
339 Views
Registered: ‎01-21-2019

FIR Compiler v7.2. After all coefficients reload over, s_axis_reload_tready will be deasserted, but how long will it be asserted?

The explanation of the s_axis_reload_tready signal in the IP Product Guide of FIR Compiler v7.2 is: tready for RELOAD channel. Asserted by core to indicate core is ready to accept data. When all coefficients are reloaded, s_axis_reload_tready will be deasserted, but how long will it be asserted? Which signals may affect the time when s_axis_reload_tready is deasserted? Through the ila debug core, after  reload is over, the time for s_axis_reload_tready to remain low is from 500us to 100ms, and the FIR clock period is 17.8ns.

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Xilinx Employee
Xilinx Employee
283 Views
Registered: ‎09-18-2018

Re: FIR Compiler v7.2. After all coefficients reload over, s_axis_reload_tready will be deasserted, but how long will it be asserted?

Hi,

The Reload_tready would be deasserted until a synchronization event happens ,which is a valid config_tdata is applied to the core. Then the channel coefficents are reloaded to the core and the compiler can start accepting new coefficients on the reload channel.

Please refer to description under Reload channel on page 18 of the FIR PG.

 

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