04-08-2019 06:09 AM - edited 04-08-2019 06:13 AM
I am using Vivado 2018.3 and Minized Board with Zynq 7z010.
I am trying to use the FIR compiler without the AXI interface. Only by generating the signals for tvalid and tready and it's not working.
If there's a project/tutorial/documentation for that?
04-09-2019 05:57 PM
04-09-2019 07:52 PM
The FIR Compiler only provides the AXI4 stream interface, it does not provide any other interface. So if you want to use FIR without AXI interface, one way is to build your own FIR filter in HDL or SysGen.
04-10-2019 08:48 AM
Thanks a lot for the advice. Know I am building the filter using, multiplicator, dff and adder.
I tried to use sysgen but I can't find a free version. Do you know where I can find the free version?
04-11-2019 02:30 AM
04-19-2019 11:01 AM
04-19-2019 07:11 PM