02-12-2016 08:30 AM
I've built an FIR filter using IP generated coefficients. When I run the testbench I see don't see any data on the output side, it's all zero. I see the impulse 400000 and 200000 getting put on the slave bus and I see TVALID on the Master side but data is all 0. In the test bench I see the ocmment about don't check the output payload as this requires the behaviroal model. Is this why there is nothing on the master AXI data bus? How does one see this? I would have thought with the impulse input that the coeffiecients would have been outputted.
02-12-2016 08:53 AM
02-12-2016 09:00 AM
could you explain what the GSR simulation is and the 100ns initialization? because I am not aware of this.
I see the impulse 400000 and 200000 getting put on the slave bus and I see TVALID on the Master side but data is all 0.
I understand the input data is correct.
In the test bench I see the ocmment about don't check the output payload as this requires the behaviroal model.
no the behavioral simulation should produce data, the post-synthesis/timing simulation is just to simulate an accurate timing model, although they are most of the time identical but that depends on the core you are simulating.
So my guess is there is a problem on your m_axis data bus handshake, try to either remove support for TREADY or provide a steady TREADY='1'
02-12-2016 09:06 AM - edited 02-12-2016 09:18 AM
could you explain what the GSR simulation is and the 100ns initialization? because I am not aware of
I'm probably not the best person to explain the minutiae of how it works; I'm only aware of it.
If you look at C:\Xilinx\Vivado\2015.4\data\verilog\src\glbl.v (which is compiled into every verilog sim), you'll see that this essentially simulates GSR circuitry and asserts a reset on everything.
So if you try to send stimulus before 100ns while GSR is asserted, you'll be sending it while the circuit is held in reset.
I've seen this alot specifically with DSP cores which is common to test with impulses. If you start generating your clock at 0ns sim time and send the impulse in on the first clock cycle to a FIR, it will be missed and the output will always be zero, as the original poster described.
If I remember correctly, this doesn't apply to VHDL simulations, though I can't remember exactly why. Maybe one of the sim folks will chime in.
At the end of the day, I just make it a habit to not do anything in my TBs until at least 100ns and don't have to worry about it.
02-12-2016 09:10 AM
02-12-2016 09:46 AM
02-16-2016 07:29 AM
I did use recently the FIR compiler v7.2 in simulation and it worked fine for me.
The first N-1 outputs are zeros, where N is the tap size of your filter.
Try to play around with the input value in your test vector, make a walking one pattern for starter.
02-16-2016 10:26 AM
Attached is the XCIX for the FIR compiler. One must rename the extention since XCIX isn't a valid extension for a compressed file (browsers complain). So simply rename the extention from .zip to .xcix and you can see what I did for the FIR filter. It's a decimation by 2, two channel FIR and I let the tool pick the coefficients (no external file).
The odd thing is the comments in the test bench that the tool generated, it specifically states you won't see anything out of the core for data. That puzzles me other than just using the simulation to look at the interface signals.
02-17-2016 11:58 AM - edited 02-17-2016 12:58 PM
Not sure why, perhaps pilot error, but this project simulation would not provide any outputs on the AXI bus. I created a new test project, added this IP from this project and it simulated correctly. Not sure why. This was 2015.4