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_underscore_
Visitor
Visitor
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Registered: ‎11-26-2019

Fir compiler resource use

Hello everyone,

I'am currently trying to use a FIR compiler with 128 coefficients and a 80 Mhz sampling and input frequency, the configuration that I am using is as presented in the joined screenshot.

The issue that I am facing is that, this configuration requires a lot of DSPs, so I thought about increasing the clock frequency => the input sampling frequency will be 80 MHz and the clock frequency will be 320 MHz, my question is : Should the clock frequency that I give to the FIR be 320 MHz or 80 MHz ? And knowing that the data that I am giving to the FIR are clocked at 80 MHz can this configuration cause any timing issues ?

Any idea or suggestion is welcome.

Thank you.

Config_summary.PNG
Config1.PNG
Config2.PNG
Config3.PNG
Config4.PNG
Config5.PNG
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1 Reply
vkanchan
Xilinx Employee
Xilinx Employee
330 Views
Registered: ‎09-18-2018

Hi @_underscore_ ,

The clock frequency should be 320 MHz  to the FIR. This will help in time sharing the DSP slices and therefore reduce DSP slice utilization

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