06-27-2017 12:58 PM
I'm working on a simple project using some Xilinx floating point ip cores (adders, subtractors, accumulators, reciprocals). The goal is to calculate pi and output the result via UART using a microblaze.
The design works fine in the behavioural and the post synthesis functional simulation however, during the post implementation functional simulation, some of the cores return completely erratic results (something like 0 + 3 = 7?!).
According to the datasheet of the core, there are no special timing constraints needed, so my timing constraints just consist of a primary clock, the automatic contraints generated by my PLL and some max delays for the RXD and TXD lines. All timing constraints are being met, there's still plenty of positive slack left.
I would be glad if someone could give a me hint how to solve this problem.
06-27-2017 01:21 PM
Vivado or ISE?
You need to look for and find the complete or verbose timing report and examine the paths not constrained. Should they be?
06-27-2017 09:47 PM
06-28-2017 11:54 AM
Thanks for the help. How should I share my project (almost 1GB of data)?
The data format is correct. Some of the cores return correct results while others don't.
By the way, I'm using a Digilent Nexys Video powered by an Artix 7 xc7a200tsbg484-3.
07-03-2017 12:43 PM
In the test bench, there is an output called "result", which should converge to a value of 0,785398 (pi / 4). This is the case in the behavioural and the post synthesis functional simulation but not in the post implementation functional simulation. All of the floating point values are represented using the IEEE754 double precision format.
I would be glad if someone could help me with this problem.