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Participant caccolillo
Participant
1,072 Views
Registered: ‎09-09-2010

HLS AND AP_FIFO IN SYSTEM GENERATOR

Hello everybody,

I've developed a simple image padder in HLS and imported in system generator/simulink design, attached with this post.In a nutshell,

I have a series of from workspace blocks to drive the hls block control inputs (ap_rst, ap_start ), to drive the data input port of the fifo and the related write enable port.

Once the fifo is filled with all the data, the ap_start is asserted, in order to start the hls block.

Problem arises for an algebraic loop error, which prevents the simulation to start (the error log is attached). 

I'm stuck with this error.

Introducing delay elements on the feedback loop somehow helps, but the hls block no longer sees correct inputs at the correct time.

Following the xapp1031 at page 21, I've introduced assert blocks on the feedback path to the fifo, but it doesn't work.

It's the only piece of literature nearest to my situation. Unfortunately, the "to ffo" and "from fifo" are no longer supported in newest system generator releases.

Does anybody have some hint about this issue?

Thanks in advance.

Any help is greatly appreciated.

 

 

 

 

schema_sysgen.JPG
error_log.JPG
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4 Replies
Participant caccolillo
Participant
1,050 Views
Registered: ‎09-09-2010

Re: HLS AND AP_FIFO IN SYSTEM GENERATOR

Struggling online, I've found this old #ar:

 

https://www.xilinx.com/support/answers/45810.html

 

in the example design they talk about the ap_fifo interface, but in the schematic there's no fifo involved.

Moreover, the feedback  "data_in_read" port toward the fifo, is left open.

It seems as if the ap_fifo interface has some issue in system generator.

Isn't it?

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Participant caccolillo
Participant
900 Views
Registered: ‎09-09-2010

Re: HLS AND AP_FIFO IN SYSTEM GENERATOR

Still searching for answers.

In WP283, at page 16-17, the author cites a block "Convert X_" to solve probably a similar issue to the mine:

 

https://www.xilinx.com/support/documentation/white_papers/wp283.pdf

 

but I cannot find the simulink schematic.

Any hint?

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Xilinx Employee
Xilinx Employee
893 Views
Registered: ‎08-01-2008

Re: HLS AND AP_FIFO IN SYSTEM GENERATOR

Can you please your design files
Thanks and Regards
Balkrishan
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Participant caccolillo
Participant
775 Views
Registered: ‎09-09-2010

Re: HLS AND AP_FIFO IN SYSTEM GENERATOR

I've found the solution on my own, after a bit of struggling.

Using the almost full flag with a delay on it, instead of the full flag, everything works smoothly.

If I had used the full flag with a delay on it, I would have incurred in the risk of losing a sample instead.

fifo.JPG
fifo2.JPG
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