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Observer
Observer
5,199 Views
Registered: ‎10-07-2009

Hardware Co-Simulation ADC/DAC Hookup with XtremeDSP Development Kit IV

Hello,

 

I am trying to create an OFDM TxRx using Sysgen 10.1 and an Xtreme DSP Kit using HW Co-Simulation.

 

My initial Tx design is the following

 

I've had no problem whatsoever reading the DAC's outputs with an oscilloscope- All data is accurate and as I want it to be

 

But now I am creating DAC to ADC hookups with 2 wired cables and the outcome on the axes is not what I wanted.

 

The outcome is the following:

 

Axes 1 and 3 is related to the IQ simulink simulation and each "set" contains 5 OFDM symbols

Axes 2 and 4 are the hardware co-simulation ones, running in Free Running mode clock at 50 MHz since I am using the ADC's.

 

Firstly and the "minor" problem (although I can't solve it) are those weird peaks. I have no idea why do they show up and to remove them

Secondly and what I've been focusing on is the output.

Initially I thought that the problem was I couldn't see anything because I am running at 50 MHz but even if I zoom in on the HW Co-sim output I can't make any sense of it

 

 

If I unhook the cables and hook the DAC to the oscilloscope I can see the signal pretty clearly.

 

Can anyone give me a hand on either these 2 problems?

 

Thanks in advance

 

-Tiago

 

 

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Xilinx Employee
Xilinx Employee
5,143 Views
Registered: ‎08-07-2007

It is important to understand the differences between "Free-running" and "single stepped" hardware co-simulation.  If you are running free-running, the board clock is used to clock the design and it will not remain synchronized with the simulink simulation (the board runs much faster than the hw co-sim communication interface).  For single stepped, the clock is driven by simulink and so remains synchronized but it is then running through layers of software and will not be a regular pulse, thus you will not see expected results on the output of your DAC and the ADC will not capture at regular intervals.

 

Please see the SysGen user guide for additional details on these.

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Observer
Observer
5,135 Views
Registered: ‎10-07-2009

First of all thanks a lot for the answer jeffreyh.

 

I did read the user guide and have a rather "ok" grasp on both clock modes.

 

Still I don't understand both things. 

 

First of the "weird peaks".

Secondly, I do understand the change on frequency when I go into free-running mode. Assuming I am acquiring the correct signal and the ADC is working correctly the problem I have is a visualization one. But still don't know how to fix it

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