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2010stone

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01-14-2011 06:33 AM

4,531 Views

Registered:
10-16-2010

How to get a vector adder block in a fast way

Hello, I´m would like to know how to get a vector adder block only using one addsub block.

I would like to create two vectors from the sets of outputs of the respectives '1ex10c1' and '1ex10c2' blocks to sum them into one AddSub block. I don´t want to add a AddSub block for every outputs pairs.

I attached my file.

Thank you so much for your help!

2 Replies

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2010stone

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01-15-2011 01:32 AM

4,511 Views

Registered:
10-16-2010

**For clarification:**

Every one of the outputs of the two blocks I put (Every one of them has 10 outputs) represent real numbers (not boolean), so I want to make a vector of ten real numbers. I want two vectors, every one of them from one 'ex10c' block to make a sum of them in the Add block.

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ywu

Xilinx Employee

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01-20-2011 02:44 AM

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Registered:
11-28-2007

In general, if you want to share logic resources, your system sampling clock has to be faster than the input sampling clock. In your particular case, the system clock needs to be 10x faster than the input sampling clock. You model doesn't have a System Generator token (by the way, the SysGen token is required for all SysGen models), I can't tell what your system clock rate is. So what's your system clock frequency and the input samping clock frequency?

@2010stone wrote:

Hello, I´m would like to know how to get a vector adder block only using one addsub block.

I would like to create two vectors from the sets of outputs of the respectives '1ex10c1' and '1ex10c2' blocks to sum them into one AddSub block. I don´t want to add a AddSub block for every outputs pairs.

I attached my file.

Thank you so much for your help!

Cheers,

Jim

Jim