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15,393 Views
Registered: ‎09-03-2009

How to get started with FFT ip core??

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I have just started to work on fft ip core, I am new to Xilinx ise, So can any one help where to get started with the fft ip core
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vytautas
Explorer
Explorer
19,546 Views
Registered: ‎10-01-2007

Hello. FFT IP core you can generate with CoreGenerator (tools of ISE).

 In this forum I have several discusion such topic about. For example here:

http://forums.xilinx.com/xlnx/board/message?board.id=DSP&thread.id=563

 I generate this pcore and try to implement it in MicroBlaze connecting per FSL bus.

Best Regards,
Vytautas

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vytautas
Explorer
Explorer
19,547 Views
Registered: ‎10-01-2007

Hello. FFT IP core you can generate with CoreGenerator (tools of ISE).

 In this forum I have several discusion such topic about. For example here:

http://forums.xilinx.com/xlnx/board/message?board.id=DSP&thread.id=563

 I generate this pcore and try to implement it in MicroBlaze connecting per FSL bus.

Best Regards,
Vytautas

View solution in original post

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15,376 Views
Registered: ‎09-03-2009

Thanks Vytautas

 

Regards

Yasir

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dudovitz
Observer
Observer
13,823 Views
Registered: ‎04-18-2012

Hey there. 

 

I've got pretty much the same problem but I actually didn't want to implement the FFT via Microblaze. Is the IpCore FFT generally a microblaze implementation or is there a possibility to just implement the FFT as a vhdl-code? 

Untill now I created a new project for the Spartan 3 FPGA ( XC3S200 ) and generated the IpCore FFT. Now I can't figure out how to use this in my vhdl-code. Does anybody know a tutorial or so? 

Thanks in advance.

 

Len 

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vlavruhin
Explorer
Explorer
13,816 Views
Registered: ‎12-08-2010

Hi, Len.


Is the IpCore FFT generally a microblaze implementation or is there a possibility to just implement the FFT as a vhdl-code?

First of all, LogiCORE IPs are designed for use in HDL projects. And FFT IP is no exception.


Untill now I created a new project for the Spartan 3 FPGA ( XC3S200 ) and generated the IpCore FFT. Now I can't figure out how to use this in my vhdl-code. Does anybody know a tutorial or so?

1. Create new VHDL project in Xilinx ISE.
2. Add 'New Source' to it. Choose IP -> Digital Signal Processing -> Transforms -> FFTs -> Fast Fourier Transform.

3. Set desired options of core and generate it.

4. Select in ISE Hierarchy View (upper left corner) your FFT core. Then in Processes View (lower) click on CORE Generator -> View HDL Instantiation Template.

5. Now you should be able to see Instantiation Template. It is file named 'YOUR_CORE_NAME.VHO'. Also you can find it manually by looking in 'YOUR_PROJECT_FOLDER\IPCORE_DIR'.

6. Add 'New Source' to the project, choose VHDL module. Insert there parts of Instantiation Template.

7. Now you can add your own testbenches and simulate core.

 

There is a detailed description of parameters of FFT IP core in following document:

http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf

Best Regards,
Vitaly.
dudovitz
Observer
Observer
13,812 Views
Registered: ‎04-18-2012

Wuhuuu there it is. Thank you very much Vitaly! Now I got something to work with. 

 

Thanks again!


Regards,

 

Len 

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valf94
Newbie
Newbie
7,011 Views
Registered: ‎01-12-2016

Hello,

I'm a student and I'm trying,for the first time, to use the core generator.

I did what you recommend but it does not work. 

 

When you say " Add 'New Source' to the project, choose VHDL module. Insert there parts of Instantiation Template."

where do i have to insert the given code? In the entity part ? In the architecture part ?

Regards

Valf

 

Here is my last try : 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fft_test is
----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
masuperfft fft_1st_test (
.clk(clk), -- input clk
.start(start), -- input start
.xn_re(xn_re), -- input [15 : 0] xn_re
.xn_im(xn_im), -- input [15 : 0] xn_im
.fwd_inv(fwd_inv), -- input fwd_inv
.fwd_inv_we(fwd_inv_we), -- input fwd_inv_we
.scale_sch(scale_sch), -- input [11 : 0] scale_sch
.scale_sch_we(scale_sch_we), -- input scale_sch_we
.rfd(rfd), -- output rfd
.xn_index(xn_index), -- output [10 : 0] xn_index
.busy(busy), -- output busy
.edone(edone), -- output edone
.done(done), -- output done
.dv(dv), -- output dv
.xk_index(xk_index), -- output [10 : 0] xk_index
.xk_re(xk_re), -- output [15 : 0] xk_re
.xk_im(xk_im) -- output [15 : 0] xk_im
);
--INST_TAG_END ------ End INSTANTIATION Template ---------
end fft_test;

architecture Behavioral of fft_test is

begin


end Behavioral;

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nagabhar
Xilinx Employee
Xilinx Employee
6,988 Views
Registered: ‎05-07-2015

HI @valf94

 

Please open a separate thread for new queries.

First of all,  you have taken a verilog instantiation template.
Use a vhdl instantiation template(.vho).
You can look up on internet on how to instantiate a module in VHDL.

Thanks
Bharath
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