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Observer fpgaioc
Observer
966 Views
Registered: ‎09-02-2015

How to set, or find out, FFT core internal frequency

Hi Expert friends,

 

I am trying to implement a streaming FFT on the zcu102 board.  Could someone advice

on the frequency stuff?  I would like to run it as fast as possible.

 

Thank you very much, best regards,

 

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4 Replies
Teacher drjohnsmith
Teacher
951 Views
Registered: ‎07-09-2009

Re: How to set, or find out, FFT core internal frequency

what do you mean by the frequency stuff ?

 

The size if each bin of the FFT ?

 

or the frequency you cna clock it at ?

 

The fist depends upon the sample rate your feeding it with,

    the second depends upon your implementation ,the part, the speed grade, and the surrounding logic.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer fpgaioc
Observer
940 Views
Registered: ‎09-02-2015

Re: How to set, or find out, FFT core internal frequency

Hi Dr John Smith,

 

Thank you very much for helping.

 

I have the zcu102 board, it has the ZYNQ UltraScale+ FPGA, -2 speed grade.  I am trying to

implement a streaming FFT, and would like to feed, and run it as fast as possible.  My question

is: how fast can I feed it?  and how can I set the internal frequency to the highest?  pg109 is

not very clear on these.

 

Thank you again, best regards,

 

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Mentor jmcclusk
Mentor
935 Views
Registered: ‎02-24-2014

Re: How to set, or find out, FFT core internal frequency

Start with a nominal clock frequency of 300 MHz..   Then run place and route, and look at your timing results.    Then modify your target frequency up or down, depending on how well you meet timing.   Go up or down in 50 MHz steps,  then 25 MHz steps, then 10 MHz steps..     Iterate until you are tired of running Vivado.

Don't forget to close a thread when possible by accepting a post as a solution.
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Teacher drjohnsmith
Teacher
913 Views
Registered: ‎07-09-2009

Re: How to set, or find out, FFT core internal frequency

Procesors have fixed clock maximums

 

FPGA's, are user defined "processing"

    

the frequency you can run at depends on the logic you put around the core, as well as the chip

 

sorry its not clear,but thats how it is,

 

try is the only way of finding out when your starting out,

   as you get more experience, you will be able to know if the frequency you want is 'easy' or 'hard' and run demos less, but you will still run demos ,,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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