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Explorer
Explorer
977 Views
Registered: ‎07-19-2012

IP Support For Little Endian

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Hi all,

 

Is there a way to enable little endian support across the entire FPGA design?

 

Or, more specifically what about the complex multiply, add and FFT Vivado IP's?

 

I'm using Vivado 2016.4 and a Kintex 7 device.

 

Thanks in advance!

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Teacher drjohnsmith
Teacher
1,183 Views
Registered: ‎07-09-2009

Re: IP Support For Little Endian

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how would you convert a 32 bit number from little to big endian ?

 

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Teacher drjohnsmith
Teacher
964 Views
Registered: ‎07-09-2009

Re: IP Support For Little Endian

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If you have a fixed width input and output,

    as in the IP cores

       then endieness is 'just' how the bits are wired 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Explorer
Explorer
959 Views
Registered: ‎07-19-2012

Re: IP Support For Little Endian

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Thanks for the reply, I see what you mean.

 

Any way to specify Endianness in the following register connection to LittleEndianPlease ?

reg [31:0]  LittleEndianPlease;

always @(posedge clk)

LittleEndianPlease <= 32'd16876;

 

 

 

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Teacher drjohnsmith
Teacher
1,184 Views
Registered: ‎07-09-2009

Re: IP Support For Little Endian

Jump to solution

how would you convert a 32 bit number from little to big endian ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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