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Newbie
Newbie
743 Views
Registered: ‎05-03-2018

Implement large delays in xilinx system generator

Hello friends, I need to delay a signal by 5ms (0.005 sec). The latency required for my delay block is 0.005/25ns =200000 as my FPGA is clocked at 25ns. I tried cascading delay blocks, but then the netlist file is not generated. Kindly help in an alternative way of implementing long delays ( of 32-bits).
Will be waiting for replies.

Thank you
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2 Replies
Advisor
Advisor
721 Views
Registered: ‎04-26-2015

What FPGA is this on?

 

In practical terms, a 200,000 cycle 32-bit delay is going to need at least 200 32K block RAMs. In the Artix 7 family, only the largest chip (the 200T) could support this. If there is external RAM then you can potentially use that, but I'm not sure whether you can do it through System Generator.

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Newbie
Newbie
695 Views
Registered: ‎05-03-2018

Hello, Thanx for the reply.

I am using zynq FPGA, it has 16 bit SRL as delay block.

(Zynq xc7z020 -1 clg484)

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