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Newbie
Newbie
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Registered: ‎05-09-2018

Implementation fails on attempt to execute hwdef in System Generator/Vivado 2018.2 and Matlab/Simulink 2018.a

I had this problem at work on a more complex design and a simple design, and thinking it may be my configuration, I came home and installed fresh and created a simple design that ended up having the exact same problem.  

Both computers are using Version 2018.2 of Vivado/System Generator and 2018a of Matlab/Simulink.  The work computer is Windows 7, the home one is Win 10 (1903).  

I generate a design in System Generator, set the Compilation target to "IP Catalog", do some other basic settings, and then click "generate" on the System Generator Block in my design.  Vivado proceeds through synthesis and implementation.  Then processing stops with an error message.  

In my simpleTest_sysgen_error file, I get:

"ERROR: An error occurred when creating the Vivado project.
invalid command name "C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/simpletest_bd_wrapper.hwdef"

INFO: [Common 17-206] Exiting Vivado at Fri Oct 11 08:39:50 2019...

...

For more information please refer to 'C:/XilinxTest/netlist/vivado.log'   "

In the vivado.log, the following appears:

"...

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: fd77bb5d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1339.965 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: SG_Analyzer -- Running impl_1 ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
[Fri Oct 11 08:39:50 2019] Launched impl_1...
Run output will be captured here: C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/runme.log
WARNING: [Common 17-259] Unknown Tcl command 'C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/simpletest_bd_wrapper.hwdef' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
ERROR: An error occurred when creating the Vivado project.
invalid command name "C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/simpletest_bd_wrapper.hwdef"
INFO: [Common 17-206] Exiting Vivado at Fri Oct 11 08:39:50 2019...  "

I can see that the "C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/simpletest_bd_wrapper.hwdef" file is present.  I went to the Vivado TCL console and tried to run it both by simply typing the file path and name, by changing directories to the file path and typing the file name, and by typing "exec C:/XilinxTest/netlist/ip_catalog/simpletest.runs/impl_1/simpletest_bd_wrapper.hwdef."  I also swapped the / for \ just to be sure.  

Since it fails, the simulation is not performed and I can't debug my design. 

However, I was able to import the IP into an example MicroBlaze vivado project and generate a bitstream.  I looked at the schematic of the implementation and it had correctly implemented the simple design that had failed to complete in System Generator.  

So the main problem is that once the failure occurs, I can't continue to use Simulink to simulate and debug my design.  

Can anyone tell me what is going on and how to fix it?  

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Moderator
Moderator
390 Views
Registered: ‎08-16-2018

Hi, 

1. Can you please share the small-design which is not working at your end. 

2. It looks the vivado project is created successfully at location "C:/XilinxTest/netlist/ip_catalog/". Can you please open the project in Vivado and generate the bitstream (to verify if it's working in this way or not). This will confirm the whether the error is coming from Vivado or SysGen. 
Note that you will need the license to generate the HDL files (it looks you already have one). 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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Visitor
Visitor
226 Views
Registered: ‎03-11-2019

Hello @tomhahaha2,

I have the exact same problem as you do and I use the same Vivado and SysGen/Matlab versions. I can generate a post-synth timing report in SysGen, but not a post-impl one. I get the same report in the log file, Tcl parser error when trying to run .hwdef file as a command.

I've tried what @meherp suggested, and I synth/impl are completed without errors. Running write_bitstream results in the following error:

[DRC HDOOC-3] Bitstream generation not allowed for OOC modules: Cannot generate bitstream for Out-of-context module implementation.

Please find both Vivado log files in the attachment, vivado.log (run within SysGen) and runme.log (run from Vivado).

Have you been able to solve this problem somehow? Thanks!

 

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