06-05-2020 05:58 PM
I am using a polyphase filter to implement a continuously variable sample rate block. I am using the FIR compiler core with 512 sets of coefficients of 23 taps each. I am using a MATLAB model as a reference and I cannot get my Vivado behavioral sim to match the MATLAB results. A few questions- (1) Does the core support 512 sets of coefficients? The documentation lists 128 sets as the max, however my core with 512 sets does not generate warnings when it is generated. (2) Can you change the selection of the current coefficient set every clock cycle via the m_axis_config_data_tdata input? (3) Is it okay to allow for multiple clock cycles per input data period to reduce DSP48 resources. Thanks for your help.
06-11-2020 02:28 AM
Hi @centercitybill ,
The FIR IP takes in quantized coefficients and also has fixed point input and output. This might not match accurately with the MATLAB model. The FIR has a MEX model which can be used in MATLAB.
For other questions,
1) The FIR compiler GUI provides the range of coefficients sets it supports This is between 1-1024. The GUI has checks to detect violations.
2) I am not sure what purpose it serves to change the config channel every clock cycle. It needs to be qualified with a data sample as well. Each data sample is operated with different filter set?
3) Yes the Hardware oversampling specifications in FIR GUI allow to specify the input sampling frequency and clock frequency. Based on this, the number of clock cycles for each input sample is shown in the same page.
06-11-2020 04:26 AM
If your goal is continuous resampling, then why use one filter selected from among multiple on a per sample rate basis? Why not just dynamically step through the filter taps given the desired resample rate?
06-11-2020 05:27 AM
Thank you for your answers. The coefficient set needs to be changed every clock cycle to implement the arbitrary rate change that I desire. An numerically controlled oscillator is used to calculate the phase delay(coefficient set) based on the ratio of the input period divided by the output period. I have chosen a polyphase filter bank to implement the variable delay in order to do the interpolation, however you can also use a Farrow structure, or mathematical interpolation. The details may be found in the following paper: 'Interpolation in Digital Modems, Part II: Implementation and Performance', F.M.Gardner, et.al., IEEE Trans. on Comm., vol.41, No.8, June 1993.
Just to verify you are saying that I can change the config channel selection every clock cycle as long as I am inputting a new data sample.
I understand the fixed point precision issues and have made my MATLAB sim fixed point to match my HDL sim. Thanks again.
06-11-2020 06:18 AM
Ahh, okay, your implementing Harris' 6th order polynomial filter, which changes coefficients based upon the incoming phase, then, right? I thought you were changing based upon frequency. Phase is easier--you just adjust where in the coefficient sequence you start your run. You also need to recover six (or is it seven?) results from the filter, one for each polynomial coefficient?
I'd personally build such an implementation by hand. Beware of truncation effects, especially when doing anything larger than a quadratic. The precision you need for a sixth order filter ... takes some work to achieve properly.
06-11-2020 06:33 AM
I am actually implementing the delay with a polyphase filter bank. I first tried a Farrow based cubic interpolator and the fidelity of the results were insufficient. It works fine for a bit timing recovery loop in a satellite modem, but I am using it on received signals that may have better than 60 dB if SNR so I decided to use the filter bank.
I agree with you assessment of paying close attention to the precision through the Farrow structure chain of multipliers. Thanks for your thoughts.