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Anonymous
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Increment/decrement counter at 2 different rates

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I want to implement a counter that I increment at the clock rate (12.5e-9 seconds) but I want to decrement the counter at different rate (1.0075e-5 seconds).  How can I implement this since the the counter block specifically asks for a single rate?

 

Can you provide a simple model file to illustrate a possible solution?

 

Many thanks for your time.

 

Ed

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vlavruhin
Explorer
Explorer
10,170 Views
Registered: ‎12-08-2010

Hi.

 

Consider that you would like to design a counter, that counts up at the frequency f1 and counts down at the frequency f2. Lets suppose that  f1 = K * f2 (K - some integer number).

 

It's really easy to describe the behavour of such counter using your favourite HDL. It should be clocked by the frequency f1. At each rising edge of f1 the counter counts up. And at each K clock cycles of f1 the counter counts down. To detect these K cycles additional counter that counts down from K to 0 can be used.

Best Regards,
Vitaly.

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

You could use the optional clock enable signal to allow the counter to increment/decrement however you'd like.

www.xilinx.com
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vlavruhin
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Registered: ‎12-08-2010

Hi.

 

Consider that you would like to design a counter, that counts up at the frequency f1 and counts down at the frequency f2. Lets suppose that  f1 = K * f2 (K - some integer number).

 

It's really easy to describe the behavour of such counter using your favourite HDL. It should be clocked by the frequency f1. At each rising edge of f1 the counter counts up. And at each K clock cycles of f1 the counter counts down. To detect these K cycles additional counter that counts down from K to 0 can be used.

Best Regards,
Vitaly.

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Anonymous
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Thanks vlavruhin, great insight.  That is all I need to get started.

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