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Observer s_aelsok
Observer
9,407 Views
Registered: ‎03-19-2012

LVDS buffer for sysgen

Hi 

I am trying to add a wrapper for LVDS input buffer in system generator. 

I tried to define that this port is an LVDS differential port in the .UCF file as follows

 

NET cha0_P LOC = "F31"|IOSTANDARD="LVDS_25" |DIFF_TERM=TRUE;

NET cha0_N LOC = "E31";

 

however i get this error massage:

-----------------------------------------------------------------------------------------------------------------

The IOB component is configured to use single-ended signaling and can not use
differential IOSTANDARD value LVDS_25. Two ways to rectify this issue are:
1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O
connectivity by instantiating a differential I/O buffer.

-----------------------------------------------------------------------------------------------------------------

Note : before that I tried to import a buffer in a blackbox, but I had an error saying that an input buffer is followed by an input buffer which is not allowed.

 

I think this is due that by the time the mapper looks at the .ucf file, it had already synthesized an single ended input buffer for the port, then in the UCF it sees that it has the constraint for LVDS. 

 

Any suggestions on how to use an LVDS port in system generator or how to tell it not to infer an input buffer before it sees the UCF file ? 

 

Thanks in advance,

Ahmed.

 

 

 

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11 Replies
Explorer
Explorer
9,362 Views
Registered: ‎12-08-2010

Re: LVDS buffer for sysgen

Hi, Ahmed.

 

Have you tried to generate the HDL netlist, import it in ISE and then setup differential port there?

Best Regards,
Vitaly.
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Observer s_aelsok
Observer
9,357 Views
Registered: ‎03-19-2012

Re: LVDS buffer for sysgen

Hi Vitaly,

I'm not sure what you mean... 

so shall I generate the HDL in sysgen and then open the resulting project file in ISE ? 

 

but then how can I import what I do in ISE back to system generator ?  as I need the JTAG cosim from system generator.

 

Thanks,

Ahmed.

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Explorer
Explorer
9,324 Views
Registered: ‎12-08-2010

Re: LVDS buffer for sysgen

Ahmed, importing the system generator netlist to ISE will allow you to add differential port and generate bitstream. But, of course, to be able to do hardware cosimulation, there should be different way.

 

As far as I see, one possible solution to this issue is to write your own top level module for system generator model and add differential buffer there. Have you tried to do it? If there are errors, could you attach your project?

Best Regards,
Vitaly.
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Observer s_aelsok
Observer
9,317 Views
Registered: ‎03-19-2012

Re: LVDS buffer for sysgen

Hi vitali, 

Thanks for your reply,

 

Now when I make the buffer in a vhdl file and import it in a blackbox , I get the following error only when I try to make the implementation target JTAG cosimulation. 

 

This happens when I define a new implementation target , which is the virtex-6 (on ML605 board) with the non-memory mapped ports (outputs on the FMC connection from the FMC150 ADC/DAC).

 

the error : 

ERROR:NgdBuild:770 - IBUF 'ibuf_CHA_N/ibuf_array[6].u1' and IBUFDS 
'adc_try_x0/adc_lvdsddr_to_sdr/adc_data_a[6].ibufds_inst' on net 
'ibuf_CHA_N_o(6)' are lined up in series. Buffers of the same direction 
cannot be placed in series.

 

when I make it for bitfile generation or HDL or NGC, it shows no error ( however, I cant co-simulate as I don't have the JTAG interface). 

 

 

 

from that, I understand that it adds an extra buffer during synthesis of the JTAG cosimulation, and the blackbox has another buffer for LVDS, so it doesnt accept having 2 input buffers in series. 

 

do you have any suggestions? 

 

Thanks for you time,

Ahmed

 

 

 

 

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Explorer
Explorer
9,293 Views
Registered: ‎12-08-2010

Re: LVDS buffer for sysgen

Hi, Ahmed.

 

I will be able to look at your project later. But at first glance, I see that you are trying to use 'Black Box' block and add there differential port. Have you tried to change the top level module instead? There is a short description of this process in the System Generator User Guide at page 327 'Providing Your Own Top Level':

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_user.pdf

 

Best Regards,
Vitaly.
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Observer s_aelsok
Observer
9,291 Views
Registered: ‎03-19-2012

Re: LVDS buffer for sysgen

Hi Vitaly,

I had a look at that , and there was something that I did not understand ... 

 

what I understood is that I have to put my whole design (LVDS buffer + other digital blocks) in a VHDL file, and then synthesize this file and  give the resulting (.ngc, .edf, .edn) to system generator through the function yourboard_postgeneration.m (which is generated by matlab when I make a new comliation target for 'yourboard').

 

What I don't understand is this part :  

------------------------------------------------

"Your top-level component must instantiate the generic JTAG hardware co-simulation top-level

component. The component instantiation must include the required clocking signals, plus any boardspecific
I/O ports your board may support."

 

first question : 

-------------------

does this mean that I have to actually write the JTAG component in vhdl? or do I have just to include it as component called

'jtagcosim_top port'

 

which has those ports : 

sys_clk : in std_logic;
cosim_clk : out std_logic;
sys_clk_buf : out std_logic;

 

and has all my input / output signals.

 

second question

-----------------------

for the rest of my design ... which is in system generator , do I have to write it in vhdl and only use the system generator for JTAG cosim ?  or could I just make 'HDL synthesis' of my other parts without the LVDS buffer , add them to the toplevel that I have to create which includes the LVDS buffer and this will be "my own toplevel" to specify in yourboard_postgeneration.m ?

 

Thank you very much for your reply,

Ahmed.

 

 

 

 

 

 

 

 

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Explorer
Explorer
9,235 Views
Registered: ‎12-08-2010

Re: LVDS buffer for sysgen

Hi. Ahmed.

 

Have you solved your problem?

 

You can try another way. When you are choosing custom target board for hwcosim generation, there is 'Settings' button. After clicking it, you can add custom 'implementation flow' parameter file with disabled additional input buffer generation.

 

 

As to your asked questions.


first question : 

-------------------

does this mean that I have to actually write the JTAG component in vhdl? or do I have just to include it as component called

'jtagcosim_top port'

 

which has those ports : 

sys_clk : in std_logic;
cosim_clk : out std_logic;
sys_clk_buf : out std_logic;

 

and has all my input / output signals.


 

As far as I understand, you should only instantiate JTAG component.

 


second question

-----------------------

for the rest of my design ... which is in system generator , do I have to write it in vhdl and only use the system generator for JTAG cosim ?  or could I just make 'HDL synthesis' of my other parts without the LVDS buffer , add them to the toplevel that I have to create which includes the LVDS buffer and this will be "my own toplevel" to specify in yourboard_postgeneration.m ?


You should be able to use previously generated netlist from model.

Best Regards,
Vitaly.
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Observer s_aelsok
Observer
9,218 Views
Registered: ‎03-19-2012

Re: LVDS buffer for sysgen

 

Hi Vitaly,

No, unfortunately I still have it ... 

 

NGDbuild in the .opt file doesnot have any command line command for not adding IOBs. 

 

What I did was I took the output vhdl/ NCD files,  I opened them in ISE added them to the project (project file is output of the synthesis) and then I removed the extra buffer, assigned its input to its output. 

and then I carried on map, PAR in ISE. 

Now I want to go back to system generator but I don't know how to do it.

I have now jtagcosim_top.vhdl , jtagcosim_top.NCD output from the ISE ... which contain the JTAG interface and my design, I would like to import that to the system generator for carrying out the hwcosimulation. 

 

any suggestions ? 

 

Thanks,

Ahmed.

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Explorer
Explorer
9,207 Views
Registered: ‎12-08-2010

Re: LVDS buffer for sysgen

Hi, Ahmed.

 

Have your tried to set jtagcosim_top as top module in _postgeneration.m?

Best Regards,
Vitaly.
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Visitor psecker
Visitor
3,779 Views
Registered: ‎11-11-2008

Re: LVDS buffer for sysgen

Hi,

We want to interface to a ML605 to an ADC/DAC board in the same way as in this thread ie. by using system generator HW co-simulation to manage a board with LVDS connections.  This thread seems unresolved.  What is the preferred method to do this ?  Where did Ahmed get to?

 

PS

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Adventurer
Adventurer
2,576 Views
Registered: ‎02-18-2014

Re: LVDS buffer for sysgen

Hi,

 

 Could there be any solution for this post? If yes, it would be really really helpful

 

Thanks,

Basil

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