Making LFM by DDS

[dariush84]

Hi

IP: DDS v4

IDE: ISE 14.7

I want to make an LFM signal(up chirp) that starts from F0=69MHz to F1=71MHz. I configure the IP core and calculate the start phase according to F0(phase0) and end phase according to F1(phase1).

I increment the phase from phase0 to phase1 and the LFM signal generated, I expected an up chirp LFM signal produced but it is a symmetric LFM signal.

Why did this problem happen? I think I configure the DDS IP Core correctly!!!

Please guide me.

Best Regards

[dariush84]

Please, answer me!!! I'm waiting.

[dariush84]

Hi

Why nobody answer? Is it a wrong question?

[markg@prosensing.com]

@dariush84 

I have not used DDSv4 to create a LFM signal – but maybe we can learn together.

I read about DDSv4 from Xilinx document DS558, which I hope you are using too.

I think the procedure for creating the LFM signal is:

1) Define the LFM: 
    F1=start frequency
    F2=end frequency
    TL=time-length of the LFM

2) Define other things: 
     FCLK = frequency of DDS clock
     FOUT = frequency output waveform from the DDS
     B = number of bits in DDS phase accumulator (see DS558)
     dP = (FOUT * 2^B) / FCLK =  phase increment value sent to DDS  (from DS558)

3) For the LFM, the equation showing how FOUT must change with running time, TR, is:   FOUT = F1 + TR * (F2 – F1) / TL

4) TR is broken into time segments.  The time-width, TC, of each segment is equal to the period of FCLK.  So, the total length of the LFM will consist of N=TL/TC time segments.  That is, the LFM consists of N time segments that are indexed by n=1 to N.

5) From 3) and 4) we can write:  FOUT = F1 + n * TC * (F2 – F1) / TL,  (n=1,N)

6) To Do:  Write HDL that calculates values of dP and feeds them to the DDS during N cycles of FCLK (causing FOUT to change from F1 to F2 in TL seconds).   That is, for (n=1,N), use equation from 5) to calculate FOUT and then use this value of FOUT in equation from 2) to calculate dP.

Cheers,
Mark

[dariush84]

Hi

I do almost the same.

1) I suppose B=48.

2) I calculate dP1 according to F1=start frequency.

3) I calculate dP2 according to F2=end frequency.

4) N=TL/TC

5) I increase dP1 until reach to dP2 by PINC that is calculated from PINC=(dP2-dP1)/N.

I expected an up chirp signal but it is symmetric. The symmetric LFM signal is true but according to DDS IP core set , I expected an up chirp signal.

Best Regards

[bruce_karaffa]

What is your clock frequency?

[markg@prosensing.com]

@dariush84 

I agree with Bruce.  Please give us the numbers for F1, F2, TL, and FCLK.

Also, describe “symmetric LFM” - maybe with a picture.

[dariush84]

Hi

Symmetric LFM signal in the time domain is as below:

Symmetric LFM

But I sweep from F1 to F2 and I expected as below:
Upchirp LFM signal

When I look at the LFM signal at the frequency domain all the things are correct!!!

B=48

F1=79.99Mhz

F2=80.01Mhz

TL=7.8ms

FCLK=210MHz

The core is in streaming mode.

My produced LFM doesn't have any problem when I look at the signal in the frequency domain,

my problem is with the time-domain signal.

Regards

[bruce_karaffa]

I assume that your expected signal is a MatLab plot and the signal has many points in each cycle of the sine wave.  What happens if you decimate the expected signal to the same sample rate as the signal you collected?

[markg@prosensing.com]

@dariush84 

For the DDS parameters you are using, I agree with Bruce that decimation will make it difficult to “see” the chirp waveform when looking at the DDS outputs.

That is, you are making a 80MHz waveform with samples taken at the 210MHz rate. That’s less than three samples per full-period sinusoid (Nyquist says we need at least two samples).  It’s hard to draw a sinusoid when you have only 2 or 3 points over a full-period of the sinusoid.

As a test, try using F1=9.99MHz and F2=10.01MHz.  Then, you’ll get at least 20 points for each sinusoid and you can easily “see” the chirp waveform - which should look as you expect.

[dariush84]

Hi

Sorry for my delay.

Thanks for your answer, I will test soon.

Best Regards

[aseelatk@gmail.com]

Hi...as part of my project i want to generate lfm signal using dds ip core in vivado..

As i am a beginner i dont have any clear idea about how to do this..

Can u please share the full vhdl code of this lfm signal..with xplanations

[dgisselq]

aseelatk@gmail.com,

This article goes over the details, equation by equation, of how a sine wave generator, such as Xilinx's DDS, works internally.  In this case, there are three basic parts: something to handle bus logic, something to generate the phase to go into the sinewave table lookup, and then the sinewave generator itself.

Further, when it comes to sine wave generation, there are several ways to do it.  The basic method of table lookup is quite simple.  If you wanted to go one step simpler, you might consider skipping the table entirely and just grabbing the MSB of the phase, or perhaps even the two MSBs of the phase--at a performance loss of course.  If you want to go more complex, you can use a CORDIC--a method known for generating sine waves without multiplies.  Sadly, CORDICs can be very logic intensive for large bit-widths.  The good news is that the DSPs available on Xilinx FPGAs provide an easy solution to the problem, so you can use linear interpolation, quadratic interpolation, or more to get roughly as good as you want.

You can find examples of all of these sine wave generation methods on line, or for simplicity just use the Xilinx DDS IP.  That said, the examples should give you an idea of how the sine wave generation section of the Xilinx DDS IP might work.

Dan

[aseelatk@gmail.com]

Can you please explain how to configure dds ip core for generating chirp signal

[dgisselq]

aseelatk@gmail.com,

It's all in the phase increment.

always @(posedge clk)
   phase_increment <= phase_increment + frequency_increment;

Dan

[bruce_karaffa]

aseelatk@gmail.com , The formula that @dgisselq gave is correct.  To expand a bit, calculate the phase increments for the starting frequency and the ending frequency.  Decide how many samples you want in your chirp.  Subtract the PI of the starting frequency from the PI of the ending frequency.  Divide this by the number of samples in your chirp.  That is the frequency_increment that Dan referred to.  Add the frequency_increment to the phase_increment on every sample.  You should get a chirp.

As an aside, it is usually better to start your own post.  That way, you can accept a solution if it answers your question.

[aseelatk@gmail.com]

Thank u for ur response..

Actually i am trying to generate a chirp signal using Xilinx dds ip core....the tool that i am using is vivado design suite.

can u please help me in configuring xiinx dds ip core for chirl signal generation

[bruce_karaffa]

Have you read the User's Guide for the DDS or the references that @dgisselq suggested?  Configure the DDS do that you can update the phase increment on each sample.  If you want an up chirp, start at teh smallest PI and increase it on each sample until you get to your highest frequency.