UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor davidab
Visitor
838 Views
Registered: ‎12-11-2017

Output TREADY disabled in System Generator FIR Compiler 7.2

I included a FIR Compiler 7.2 block in my design using System Generator, and I want to package it to integrate in Vivado 2015 with other blocks using an AXI Stream interface.

 

However, the block does not present the output TREADY. Going to the block options, in the Interface tab the option is greyed out.

fir options.PNG

In the documentation it says that I should tick that option to present the port, so it can support back pressure, but it does not say what to do to enable the option.

 

Questions:

- How can I enable the TREADY option?

- If it is not possible, how does the FIR Compiler 7.2 block implement the AXI Stream bus?

- How can I integrate this design with other blocks in Vivado using AXI Stream bus?

 

Thanks,

Tags (3)
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
820 Views
Registered: ‎08-01-2008

Re: Output TREADY disabled in System Generator FIR Compiler 7.2

data_tready is not optional signal . Its always enable with FIR block .

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
tt.png
0 Kudos
Visitor davidab
Visitor
805 Views
Registered: ‎12-11-2017

Re: Output TREADY disabled in System Generator FIR Compiler 7.2

Thanks for your answer.

However, that is not what I was looking for. The signal you highlighted is the output signal from the FIR block to indicate its feeding block whether it can receive more data or not. The upstream block should have an input to receive that signal to implement the protocol. In the same fashion, the downstream block in the chain will generate its own "tready" signal, which should be received by the FIR block.

 

What I am missing is that "tready" input in the FIR block to receive the signal from the sink.

 

Looking in the IP block in Vivado, you can enable that input port easily. Is that a bug in the System Generator?

 

How can you implement the AXI protocol? Also, how can we receive the "tvalid" signal from the source?

 

Regards,

0 Kudos