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Registered: ‎03-05-2012

Porting Spartan-6 distributed logic filter to Spartan-7

Hi

I have an existing design for Spartan-6 that uses FIR compiler v5.0 to generate a distributed arithmetic FIR filter. I am looking to port this to Spartan-7, but have the following problem:

 - Spartan-7 isn't supported by ISE so I need to move to Vivado. OK.

 - Vivado doesn't have FIR compiler 5.0, but FIR compiler 7.2. OK.

 - Distributed arithmetic support was removed after v5.0. Why?!!

I hear that this is an internal decision, and obviously isn't going to change any time soon.

Is there any other way of porting this filter? I saw a post suggesting that the filter netlist could be generated in ISE then loaded into Vivado (https://forums.xilinx.com/t5/DSP-IP-and-Tools/FIR-compiler-tools-general-info/m-p/775786/highlight/true#M1293). Would it be possible to elaborate on how to do this?

 

Thanks

Will

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