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Visitor
Visitor
11,476 Views
Registered: ‎12-31-2007

Problem with DSP tools 9.1

Hi,
I'm using DSP tools 9.1 with ISE 9.2 and Matlab 2007. I'm using th Black Box block tp import a verilog function to the system. When using a ModelSim Verilog installation, i get a simulation error "cann't find unisim library and vcom". And when using a ModelSim VHDL installation, i get an ellaboration error "A design must be loaded before the find command can be used" and a warning at compilation "Warning: [1] mult_test_cosim.vhd(1809): A use of this default binding for this component instantiation will result in an elaboration error."
 
Can any one help me.
 
I have another question, how can i get an older version of System Generator. I need System Generator 6.1 it was working great.
 
Thank you,
Enas Ashraf
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Xilinx Employee
Xilinx Employee
11,467 Views
Registered: ‎08-07-2007

For a Verilog HDL black box that uses Xilinx primitives, under the "Advanced Tab" of the ModelSim block you must check the box "Include Verilog UNISIMS Library".

The error when using VHDL appears to be related to a syntax error.  If you'd like further assistance with this please open a webcase with Xilinx Technical support here:
http://support.xilinx.com/support/clearexpress/websupport.htm
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Visitor
Visitor
11,442 Views
Registered: ‎12-31-2007

Hi,
Thanks for the reply. I did as mentioned and forced using Verilog unisim library, but i still have this error :
 
# ** Error: (vcom-19) Failed to access library 'unisim' at "f:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim".
# No such file or directory. (errno = ENOENT)
# ** Error: mult_test_cosim.vhd(1410): Library unisim not found.
# ** Error: mult_test_cosim.vhd(1411): Unknown identifier 'unisim'.
# -- Loading package conv_pkg
# ** Error: mult_test_cosim.vhd(1416): VHDL Compiler exiting
# ** Error: f:/Modeltech_xe_starter/win32xoem/vcom failed.
 
it seems a vhdl code is generated though in xilinx block i'm generating verilog code
is there any way to avoid this vhdl code??
 


Message Edited by enas_ashraf on 01-04-2008 07:09 AM

Message Edited by enas_ashraf on 01-04-2008 07:10 AM
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Xilinx Employee
Xilinx Employee
11,434 Views
Registered: ‎08-02-2007

It sounds like a configuration problem with ModelSim.  I would check to make sure that you have the correct pre-compiled simulation libraries for XE and that the modelsim.ini file is referencing the correct library locations.  You can find the latest pre-compiled libraries here: http://www.xilinx.com/support/download/i92winmxe.htm

Another approach to troubleshooting would be to make sure you can perform a behavioral simulation outside of System Generator for DSP.  I would create a quick ISE project and see if you can simulate that.

If these two things fail, I would suggest opening up a Xilinx Technical Support Webcase: http://support.xilinx.com/support/clearexpress/websupport.htm
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Visitor
Visitor
11,425 Views
Registered: ‎12-31-2007

Hi,
Thanks fo help. Here are the results i have:
1. System generator generates VHDL files, so to simulate a design with Verilog portion, i should have a ModelSim mixed mode license. I got ModelSim SE with this mixed mode license.
2. Some of the errors were eliminated but i still have this error
 
# ** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
# No such file or directory. (errno = ENOENT)
# ** Error: F:/..../Modeltech/win32/vcom failed
.
 
So i guess as you said it's missing libraries.
 
I'm using Xilinx ISE 9.1i and DSP tools 9.2.0i and ModelSim SE PLUS 6.1c. What about this combination, i'm afraid they are not compatible ??
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Xilinx Employee
Xilinx Employee
11,407 Views
Registered: ‎08-07-2007

All Xilinx tools should be the same version number.  For instance, System Generator 9.2 should be used with ISE 9.2 with all the latest service packs.  For details on supported tools for System Generator take a look at answer record 17966:
http://www.xilinx.com/support/answers/17966.htm

However I don't believe this is the cause of your errors in this case.  It looks as though you haven't compiled the UNISIMS libraries for simulation of Xilinx primitives.  To do this go to your Start menu and launch Xilinx ISE > Accessories > Simulation Library Compilation Wizard.  Here you'll specify your simulation tool, languages, devices and libraries.  It's safe to just select all for compilation. 
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Xilinx Employee
Xilinx Employee
11,404 Views
Registered: ‎08-02-2007

I also would double check your path variable.  The first reference to ModelSim in the environmental $path variable will be the one that is picked up.

I had assumed that you were using ModelSim XE from a previous error message:

# ** Error: mult_test_cosim.vhd(1416): VHDL Compiler exiting
# ** Error: f:/Modeltech_xe_starter/win32xoem/vcom failed.

But you now mention using ModelSim SE.
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Visitor
Visitor
11,322 Views
Registered: ‎12-31-2007

Well, it's true that i used ModelSim XE at the beginning, but when i had the problem of system generator generating VHDL code and that a mixed mode license is needed, i switched to ModelSim SE or PE as i have a mixed mode license for them.
 
I'll try compiling the simulation libraries and check.
Thank you
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