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Participant 2010stone
Participant
4,532 Views
Registered: ‎10-16-2010

Problems with CORDIC block at getting the bistream file

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Hi all, I don´t get to get the bitstream file. I have an several errors when I try to generate the bitstream file. The error

enter image description here

I have this error message from the file call 'xflow.results':

ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary follows. This summary will show a MINIMUM net delay for the paths. The "Actual" delays listed in this summary are the UNROUTED delays with a 100 ps timing budget for each route, NOT the achieved timing. Any constraint in the summary showing a failure ("*" in the first column) has a constraint that is too tight. These constraints must be relaxed before PAR can continue. Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify the problem paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.

This is strange to me because I have never had a constraint problem.

Does anybody know what I could do, to avoid constraint problems in system Generator? Thank you so much.

The link for my .mdl file:https://www.dropbox.com/s/h15ns3p55wlbuc2/singledivider_exampleconceptlatencyandsimtime.mdl

The link for my xflow. file: https://www.dropbox.com/s/odqoakbrs21ngbx/xflow.results

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Instructor
Instructor
5,390 Views
Registered: ‎08-14-2007

Re: Problems with CORDIC block at getting the bistream file

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From the .results file you can see the timing constraint:

 

 

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_clk_7a10daec = PERIOD TIMEGRP "clk_7a1 | SETUP   |    -8.241ns|    18.241ns|      14|      110254
  0daec" 10 ns HIGH 50%                     | HOLD    |     0.188ns|            |       0|           0
------------------------------------------------------------------------------------------------------

It seems that you're trying to run at 100 MHz, but the best case would be closer to

55 MHz.  There are only 14 timing errors, meaning that it's likely that the CORDIC

core itself can run at 100 MHz, but you probably need to have pipelining at the

input or output to help meet timing.  As suggested you should look through

the post-map timing report and see if you can decipher where the worst-case

paths are.

 

-- Gabor

-- Gabor
3 Replies
Scholar drjohnsmith
Scholar
4,526 Views
Registered: ‎07-09-2009

Re: Problems with CORDIC block at getting the bistream file

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it asks you about the timing constraint,

 

what have you that set to ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Instructor
Instructor
5,391 Views
Registered: ‎08-14-2007

Re: Problems with CORDIC block at getting the bistream file

Jump to solution

From the .results file you can see the timing constraint:

 

 

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_clk_7a10daec = PERIOD TIMEGRP "clk_7a1 | SETUP   |    -8.241ns|    18.241ns|      14|      110254
  0daec" 10 ns HIGH 50%                     | HOLD    |     0.188ns|            |       0|           0
------------------------------------------------------------------------------------------------------

It seems that you're trying to run at 100 MHz, but the best case would be closer to

55 MHz.  There are only 14 timing errors, meaning that it's likely that the CORDIC

core itself can run at 100 MHz, but you probably need to have pipelining at the

input or output to help meet timing.  As suggested you should look through

the post-map timing report and see if you can decipher where the worst-case

paths are.

 

-- Gabor

-- Gabor
Participant 2010stone
Participant
4,507 Views
Registered: ‎10-16-2010

Re: Problems with CORDIC block at getting the bistream file

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Yes, I ´ve realized that if I change the time in the Token block and put in the parameter of FPGA clock period, 50 ns. I get to finish the compilation process and I get the .bit file.

Thank you.:smileyhappy:

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