cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chili.chips
Participant
Participant
1,202 Views
Registered: ‎09-01-2014

RF-Analyzer

Jump to solution

What is the significance of 'Clocking Reference' box?

 The value seems to be auto-calculated by the tool, and we could not figure out what it was supposed to convey. At times, it simply mimics our 'Tile Clock Input' value, though for most part it would land on 1230.00MHz or 50.00MHz for our 3000.00MHz input.
 
   We understand that the tool is still in the early stages of development -- Pls. advise if we are trying to read too much into that little box...
Clocking Reference BoxClocking Reference BoxMaturityMaturity
0 Kudos
1 Solution

Accepted Solutions
chili.chips
Participant
Participant
1,096 Views
Registered: ‎09-01-2014

could you please take a quick look at RFDC-Eval posting

https://forums.xilinx.com/t5/DSP-IP-and-Tools/RFDC-Eval/m-p/944402?advanced=false&collapse_discussion=true&filter=location&location=forum-board:dspip_tools&q=RFDC-eval&search_type=thread

on this forum and advise on how to overcome communication error with board that has been modified for external clock.

View solution in original post

0 Kudos
6 Replies
fernandovives
Adventurer
Adventurer
1,178 Views
Registered: ‎12-16-2018

Hi

The reference clock is the clock signal that is used to generate all the remaining clock signals in your design through PLLs or clocks dividers depending on the target frequency of those clocks, and the availability of this resources in your system. This main clock can be obtained from a onboard oscillator or from a external oscillator that can be supplied in the board through a SMA connector or anything other clock port.

I hope that this information was useful to you. If you think that this answer solve your question let me know.

0 Kudos
chili.chips
Participant
Participant
1,166 Views
Registered: ‎09-01-2014

Thanks, that's understood.

  We are in this case using 'external clock modification' to bypass on-board clock generators from TI. That means that the clock is coming from SMA on the XM500 card.

  We have also, using RF-Analyzer GUI option, bypassed the PLL within FPGA... meaning that our externally-supplied clock is not Reference, but rather the full-rate Sampling Clock. We have set the external clock generator to 3000.00MHz and typed that setting into 'Tile Clock Input' box in RF-Analyzer GUI. The clock is recognized and GUI display ClockDetected status. We can generate waves with DAC and aquire them with ADC. Things are nice and dandy.

  The only remaining question is about 'Clocking Reference' box in the RF-Analyzer GUI. We tried typing 3000.00MHz into it. The GUI in most cases overrides our typed-in value with 1230.00MHz or 50.00MHz. There were however few cases when the GUI left our 3000.00MHz entered there intact.

   Q1) What's the purpose of that box?

   Q2) Is the user expected to type in frequency set on the external clock generator into it?

   Q3) Is there a known stabilty issue with that box?

   Q4) What differentiates 'Clocking Reference' from ''Tile Clock Inputbox?

0 Kudos
fernandovives
Adventurer
Adventurer
1,151 Views
Registered: ‎12-16-2018

Hi 

A1)The clocking reference tab is used to calculate reference spurs for the FFT graph of the ADC.

A2) If you are using a embedded PLL the reference clock is automatically calculated by the program.

A4) The tile clock input is the reference frequency of the embedded PLL when this feature is enable, if the PLL is disable then the frequency of this clock is the sampling frequency of this tile.

I also suggest you that also check the ug1309 document. I hope that this information was useful to you.

UG1309 LINK:

https://www.google.com/url?sa=t&source=web&rct=j&url=https://www.xilinx.com/support/documentation/user_guides/ug1309-rf-data-converter-interface.pdf&ved=2ahUKEwiF35-3y9zgAhVkp1kKHeWSAzEQFjAAegQIAhAB&usg=AOvVaw34t22_nklXRFMTu1ufol5

 

chili.chips
Participant
Participant
1,132 Views
Registered: ‎09-01-2014

Thank you, that fully answers our original question!

Then, to increase the utility of RF-Analyzer tool in our evaluation, we need help with two additional items:

i) Can you provide bit file with larger BRAMs, for the sample size of at least:

       - ADC: 16K samples

       - DAC: 64 samples

ii) Is there an updated or internal version of RF-Analyzer tool that allows setting DAC current to 32mA. Existing tool version displays that button, but won't change away from 20mA.

We understand that the RFDC-Eval would have been better tool for these two features, but have found it incompatible with external clock mod -- Pls. look for 'RFDC-Eval' topic on this forum for more on that...

need 32mA/3.0V modeneed 32mA/3.0V modeneed 64K samplesneed 64K samples

0 Kudos
fernandovives
Adventurer
Adventurer
1,115 Views
Registered: ‎12-16-2018

Hi

The RF analyzer tool is used to test the Xilinx ZYNQ RFSoC. The RF data converter EVALUATION TOOL provides more features like the use of external DDR memory with up to 64 M samples. The RF analyzer only support BRAM memory mode. I don't know if exist another version of ththe RF Analyzer that allows the power options that you need.  

chili.chips
Participant
Participant
1,097 Views
Registered: ‎09-01-2014

could you please take a quick look at RFDC-Eval posting

https://forums.xilinx.com/t5/DSP-IP-and-Tools/RFDC-Eval/m-p/944402?advanced=false&collapse_discussion=true&filter=location&location=forum-board:dspip_tools&q=RFDC-eval&search_type=thread

on this forum and advise on how to overcome communication error with board that has been modified for external clock.

View solution in original post

0 Kudos