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sha2
Contributor
Contributor
1,008 Views
Registered: ‎07-07-2019

RF SoC NCO freq hopping

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Hi everybody

the subject is about the RFSoC RF converter IP

has someone perform any check about the NCO update dedicated ports ?

I am interested to know the following :

On page 137 of the spec joined here there is a figure that describe the NCO update via dedicated ports 

1.    whats the max update rate on those ports ? Can we know whats the values T1 , T2 ?  if its depend in others parametters , so can you refer us to a more detailed spec ? 

2.    when the ports are busy is the NCO previous configuration stable ? 

3.    After a NCO update , how can we know to which NCO values the IP samples outputs  are related ? I mean , is there any indication (fixed latency , trig ports or whatever else  ) 

Thanks

Sha2

 

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klumsde
Moderator
Moderator
924 Views
Registered: ‎04-18-2011

Hi @sha2 

This feature is for managing frequency hopping. 

It is expected that with this we can hop the frequency once every 1us. 

T1 is there to illustrate the time from a request to the busy signal asserting. In this case there is the added condition that the logic will wait for the IP startup state machine before asserting busy / starting the writes. 

T2 is variable and depends on the number of writes you are doing. In this case each register write takes 5x s_axi_aclk cycles. 

During the update the previous Phase/Freq are still valid. The new values are applied when busy goes low. 

 I am not sure what you mean in question 3. If you have a case where your tiles are aligned then you have the sysref mechanism to manage the update. 

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klumsde
Moderator
Moderator
925 Views
Registered: ‎04-18-2011

Hi @sha2 

This feature is for managing frequency hopping. 

It is expected that with this we can hop the frequency once every 1us. 

T1 is there to illustrate the time from a request to the busy signal asserting. In this case there is the added condition that the logic will wait for the IP startup state machine before asserting busy / starting the writes. 

T2 is variable and depends on the number of writes you are doing. In this case each register write takes 5x s_axi_aclk cycles. 

During the update the previous Phase/Freq are still valid. The new values are applied when busy goes low. 

 I am not sure what you mean in question 3. If you have a case where your tiles are aligned then you have the sysref mechanism to manage the update. 

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GuyDorman
Newbie
Newbie
412 Views
Registered: ‎10-14-2020

Hi,

I am also interested in frequency hopping capability in my application.

Can you please let me know which application are you designing with the RFSoC which needs frequency hopping?

Thank you,

Guy

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