10-20-2010 10:53 AM
I'm also having trouble with this core. I'm not getting any output on any of the pins. Even the RFD pin (which I'm assuming should be high as soon as the model is initialized) is undefined. I attached a screenshot of what I'm doing. Any help would be appreciated.
11-29-2010 06:36 AM
please have a look at the http://www.xilinx.com/support/documentation/ip_documentation/ug745_viterbi_decoder.pdf
which is the user guide for the Viterbi. Even though there are not any sysgen design the HDL examples shoould hopefully give you a clue on what your issue may be
11-30-2010 02:11 AM
I had a similar problem with the Reed Solomon cores. You will either need an evaluation license or a full license of the cores in order to use them in SystemGenerator, even in simulation mode.
11-30-2010 06:34 AM
I would recommend you to create case with Xilinx Tech Support. The issue might be with axis property.
Make sure you have eval or full license for Viterbi. In sysgen library block with green color need license
12-09-2010 08:52 AM
It turns out it was a licensing issue. I don't know why the block did not just throw a licensing error. All other green blocks I've tried to use have thrown an error when attempting to use it without the license. Very frustrating. Can any Xilinx employee explain why this block would not throw an error like other blocks? Basically I want to avoid sinking time into this issue with other blocks. How do you tell if the license actually exists and is being recognized properly?