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olufola
Observer
Observer
3,514 Views
Registered: ‎02-01-2012

Relaxing default timing constraints for HW Cosim

Hi Everyone,

 

I designed a pulse shaping circuit model using System Generator for DSP but it is not meeting one of the default timing constraints during HW Cosimulation. My design can tolerate a much relaxed timing constraint  and its not as tight as that imposed by default. I think the obvious solution is to edit the defualt constraint file after backing it up. 

 

I could not locate the the default constraint file SysGen uses. I need to know where the default value for the failing constraint is specified for me to relax it. A screenshot of the the Sysgen hwcosim par report is attached.

 

Thanks.

hwcosim_par_report.png
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chrisar
Xilinx Employee
Xilinx Employee
3,506 Views
Registered: ‎08-01-2007

The constraints are set at in the clocking tab of the System Generator for DSP token.


Then anything that runs at a slower rate handeled with multi-cycle path constraints.

 

The constraint you slected though seems to be associate with a MMCM block.  These constraints are most likely generated by putting a constraint on the input of the MMCM block, and the tools then auto generateing the output constraints.

 

This is because the design is a HW-CoSim design.  When targeting HW-Cosim, you can't change the clock, as it is tied to a board, and is needed to make sure that the interface between the board and software is working correctly.  So you can not change it.

 

You could greate a custom JTAG HW-CoSim target that uses a differnt clock, even if it is for an existing board.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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olufola
Observer
Observer
3,502 Views
Registered: ‎02-01-2012

Hi Chris,

 

You suggested that I should create a custom hwcosim target. Is there a primitive to do that or do I have to start from scratch? 

 

Thank you.

 

 

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