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Participant
7,729 Views
Registered: ‎10-16-2010

## Semantic error in Mult

Hello, I have the next problem (see the image). The question is why 3*4 = 6?

The parameters of my mult block are:

Precision: Full

Latency: 3

The parameters of my constant block are:

Type: Signed(2´s comp)

Constant value: 3

Number of bits: 16

Binary point: 10

Tags (3)
8 Replies
Visitor
7,721 Views
Registered: ‎06-11-2010

1. Make sure your 'gateway in' parameters are set up correctly. (number of bits and binary point as well as siged or unsigned)

2. Make sure the multiplier output precision is also correct.

3. If the blocks are interpretting the data as signed integers then the output is the complement.

4. The multiplier has a latency of 3 clock cycles. Make sure you run the model for at least 3 cycles to fill the pipeline.

Participant
7,716 Views
Registered: ‎10-16-2010

Sorry , I don´t understand the relation between the concept of latency and the concept of pipeline?

I set up the latency as 1 but I get the same result.

Visitor
7,712 Views
Registered: ‎06-11-2010

The pipeline is the internal digital logic performing the computation, The pipeline is typically divided into multiple stages in order to increase throughput when performing the same operation a large number of times. By default, the multiplier has a pipeline of 3 stages (latency = 3). This just means it will take 3 clock cycles before the multiplier produces the result you are looking for.

Run the model using a 'to workspace' block and look at the output in the Matlab worksapce. You will be able look at the first few time steps and see how it takes 3 cycles before it produces the product. Since you have constants as inputs, It will compute a product and hold it. Try changing the inputs and you will notice how the correct product lags the inputs that produced it by 3 time steps.

First, you need to check your block parameters to ensure they are performing as desired. Try using unsigned integers as inputs with binary point at 0 and set multiplier output to full precision to start. This will make debugging earsier. SysGen gets tricky when using signed arithmetic since it is 2's complement.

Xilinx Employee
7,710 Views
Registered: ‎11-28-2007

It will help if you attach the model file (.mdl file) instead of just a snapshot of it.

@2010stone wrote:

Hello, I have the next problem (see the image). The question is why 3*4 = 6?

The parameters of my mult block are:

Precision: Full

Latency: 3

The parameters of my constant block are:

Type: Signed(2´s comp)

Constant value: 3

Number of bits: 16

Binary point: 10

Cheers,
Jim
Visitor
7,704 Views
Registered: ‎06-11-2010

Attach the model

Participant
7,660 Views
Registered: ‎10-16-2010

I´ve just attached my file.

Participant
7,657 Views
Registered: ‎10-16-2010

I´ve put as unsigned, the constant block, the input block and the mult block and I get 12 at the output block.

:smileyhappy:

Xilinx Employee
7,543 Views
Registered: ‎11-28-2007

Just wanted to point out what went wrong in your original model: the "Gateway In' block is set to signed 16.14 format with saturation, which means the output of the "Gateway In" block is bound to [-2, 2). When you send "4" to the "gateway in" block, it saturates the block and the down stream logic only sees 1.9999... . This is why you get "6" as the result. If you change the "Gateway In" data to signed 16.12 format, you will get the expected result 12.

If you don't expect overflow occuring in your design, it's always a good idea to use "Flag as error" as the "Overflow" option for a block.

@2010stone wrote:

I´ve just attached my file.