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manganganath
Observer
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Registered: ‎07-13-2009

Simple FIR filter with XSG

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Hello,

 

I want to implement a FIR filter with basic delay, adder and multiplier blocks. I tried a very simple design, but I couldn't generate the HDL Netlist file because of some errors though simulations working correctly. Can some one plese help me with this design.

I have upoaded it here: http://www.ent.mrt.ac.lk/~060125p/files.html (Right click on the link and select "Save link as")

 

Thank you.

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manganganath
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Registered: ‎07-13-2009
Finally, I found that it's a problem with Xilinx core. I could generate both VHDL/Verilog codes and board specific hardware co-simulation block after selecting "use behavioral HDL" in "implementation" tab of the Xilinx blocks.

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manganganath
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Registered: ‎07-13-2009

This is the error log file:

 

 

--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 10.1.3.1386            D:/Xilinx_10.1/DSP_Tools/common/bin/../../sysgen
AccelDSP 10.1.3.1386                    D:/Xilinx_10.1/DSP_Tools/AccelDSP
Matlab 7.6.0.324 (R2008a)               C:/Program Files/MATLAB/R2008a
ISE 10.1.03i                            D:/Xilinx_10.1/ISE
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
     Block: Unspecified
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  Unspecified

Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't run
d:/xilinx_10.1/ise/bin/nt/coregen.exe: 1 at
F:\FYP\Work\XilinxSysgen\FilterTest\netlist1\sysgen\masterScript32498.pl
line 356

--------------------------------------------------------------------------------

 

Is this because of missing of some library files?

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ywu
Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

Just curious, if you open a dos command window, can you run "coregen" from there (just to check if coregen.exe is in your PATH and it runs correctly standalone)?

 

Cheers,

Jim

 

Cheers,
Jim
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manganganath
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Registered: ‎07-13-2009
Yes, Coregen works correctly standalone...
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manganganath
Observer
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6,357 Views
Registered: ‎07-13-2009
Finally, I found that it's a problem with Xilinx core. I could generate both VHDL/Verilog codes and board specific hardware co-simulation block after selecting "use behavioral HDL" in "implementation" tab of the Xilinx blocks.

View solution in original post

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prem_dreams4u
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Registered: ‎08-24-2009

nbothing like that. i was able to generate hdl from ur model without any difficulty.

need not even implement using behavioural model in implementation tab

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