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529 Views
Registered: ‎06-07-2019

Simulating Soft-Decision FEC using Modelsim

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I have been working with the LDPC Encoder/Decoder IP core in a design for a while, and have a functional design and simulation testbench working with an RFSoC. I am trying to instead use the Soft-Decision FEC IP core to take advantage of the hard-baked silicon available in the RFSoC.

The my SD FEC testbench in Modelsim produces Xs for dout (even when simulating the netlist). The example project for the IP core has the same problem. If I run the example project in the Vivado simulator, I get meaningful output from the encoder dout.

Are there special requirements I am missing for simulating this particular IP core?

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vkanchan
Xilinx Employee
Xilinx Employee
458 Views
Registered: ‎09-18-2018

Hi richard.muri@ll.mit.edu 

Which Modelsim version is being used ? If it is 10.7c then there is a problem in how the values are displayed in the waveform. 

Please use a version earlier or later than 10.7c i.e either 10.6c or Modelsim 2019.2 to avoid this issue.

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vkanchan
Xilinx Employee
Xilinx Employee
459 Views
Registered: ‎09-18-2018

Hi richard.muri@ll.mit.edu 

Which Modelsim version is being used ? If it is 10.7c then there is a problem in how the values are displayed in the waveform. 

Please use a version earlier or later than 10.7c i.e either 10.6c or Modelsim 2019.2 to avoid this issue.

View solution in original post

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443 Views
Registered: ‎06-07-2019

I was using Modelsim 10.7c. For future users with similar issues, I resolved my problem by switching to Modelsim 2019.3. This appears to be a bug in Modelsim.

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