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Visitor mmesan
Visitor
682 Views
Registered: ‎08-03-2018

Simulation/Verification of FFT IP core results

Hi everyone,

 

I have placed FFT IP core (v9.0) in my design, but I don't know how to check its results.

In the documentation is stated how to debug AXI-Stream Interface (page 95, https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf ), but when I place ILA in my design, I can not see any results.

 

If anyone can guide me, that would be great!

Thanks in advance.

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Scholar dpaul24
Scholar
668 Views
Registered: ‎08-07-2014

Re: Simulation/Verification of FFT IP core results

@mmesan,

Unfortunately you have given very little data on what is happening.

 

It is always better to check if your design is working in simulation. Is this working *as expected* there?

Check out the AXIS signals of the IP core in sim first.

 

but when I place ILA in my design, I can not see any results.

An ILA core can come in when you have generated the bitstream and you see abnormal behavior on the real hardware/FPGA.

 

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Visitor mmesan
Visitor
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Registered: ‎08-03-2018

Re: Simulation/Verification of FFT IP core results

Hi @dpaul24,

 

Thanks for your answer and time :)

Sorry for not being clear about my question.

So, I have FFT IP core in my design, and I tried to collect the results using ILA IP core (I don't know if I have done that proper way, but I have attached that part of my block design). Then I re-generated bitstream, exported hardware to SDK. Programmed board, and ran application. In the screenshot is waveform of ILA IP core which is connected to m_axis_data_tdata[31:0].

So my question is how can I collect results of FFT using ILA, or maybe other way so I can check if it is calculated properly? I am doing FFT of an audio signal in real time, at least I want to do so.

I have seen topics where people use FFT IP core and post their results, but I couldn't find the way how to plot my results.

 

Hope I have explained my problem well,

Thanks in advance,

bd.png
ila.png
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Scholar dpaul24
Scholar
640 Views
Registered: ‎08-07-2014

Re: Simulation/Verification of FFT IP core results

@mmesan,

 

But I asked you a counter question, I repeat....

It is always better to check if your design is working in simulation. Is this working *as expected* there?

Check out the AXIS signals of the IP core in sim first.

 

Programmed board, and ran application.

Before running it on real hardware, are you sure your design works as you expect it to be in simulation?

If you don't make this sure, it is very difficult to debug in hardware.

My advice would be to check the AXIS signals using simulation before debugging it in hardware using ILA core.

 

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Scholar dpaul24
Scholar
638 Views
Registered: ‎08-07-2014

Re: Simulation/Verification of FFT IP core results

Moreover I see problems in your BD.

 

Your master side AXIS signal is not being driven. If the TREADY is not being driven from the master side, it will not be passed to the slave for handshake and so slave will provide any AXIS data (tdata & tvalid & tlast).

Connect a suitable AXIS master and then try out. the ILA core should look like a tap-out of the master_AXIS signals.

 

Brush up your fundamentals on AXIS and read carefully how an ILA core works.

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