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Adventurer
Adventurer
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Registered: ‎01-30-2018

Strange behaviour in LogiCORE IP Multiplier v11.2

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Hi guys, I'm using one LogiCORE IP Multiplier v11.2.

I've created a simple testbench to check its behaviour and this is what I'm getting.

 

I change both inputs at the same time, however, it created an intermediate value which ruins my design.

 

Can anyone explain me why is happening this? How can I avoid those intermediate values?

 

ISIM 

Thanks in advance!

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867 Views
Registered: ‎06-21-2017

Re: Strange behaviour in LogiCORE IP Multiplier v11.2

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There is obviously one more register delay in the b path than in the a path.  You have options.  You can instantiate the DSP48 slice and control all of the registers directly, you can change your design to grab the multiplier output only on the clock cycle two clocks after changing the input or you can add a register before the a input of your multiplier. 

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868 Views
Registered: ‎06-21-2017

Re: Strange behaviour in LogiCORE IP Multiplier v11.2

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There is obviously one more register delay in the b path than in the a path.  You have options.  You can instantiate the DSP48 slice and control all of the registers directly, you can change your design to grab the multiplier output only on the clock cycle two clocks after changing the input or you can add a register before the a input of your multiplier. 

View solution in original post

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Registered: ‎06-21-2017

Re: Strange behaviour in LogiCORE IP Multiplier v11.2

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One more possibility is to just multiply in your code.  The multiply operator is synthesizable.  Just put it in a registered process and put a register before and after the multiplier too.  

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