Strange problem with System Generator FIR Compiler 7.2
We are experiencing a strange behaviour with the FIR Compiler block (v7.2) in System Generator. In certain bitstreams the IP does not give output signal (checked with ChipScope) even if the rest of its signals are correct. Sometimes, just re-synthesizing the Vivado project in which the IP generated with System Generator is instantiated (without changing any parameter on the IP or the project), the new generated bitstream works… other times it continues not working.
The IP is configured as “Single_rate”, 1 channel, 1 path, with the “Maximum_possible” Oversampling, Symmetric coefficients, “Systolic_Multiply_Accumulate” architecture and Speed goal. We use 110 coefficients.
We have checked that all the generated timing constrains by SystemGenerator have been properly imported into the Vivado project and that the generated implementations meets timing.
Is there any known bug that could explain this behaviour? Any clue on how to solve it?