Hi all, I was wonder if there is any documentation or guide that contains the most comon errors that users make in the diagram modelling stage of System Genertor.
Other similar point would be a guide with the most representative case of errors for every xilinx block.
Thank you so much for your help.
I'm not aware of any documenation like this.
The main issue you will see is that user mismatch sizes or data types. Or rate mismateches on multi-port blocks.