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Participant
Participant
2,742 Views
Registered: ‎10-16-2010

Summary of frequent errors at design-modelling stage

Hi all, I was wonder if there is any documentation or guide that contains the most comon errors that users make in the diagram modelling stage of System Genertor.

 

Other similar point would be a guide with the most representative case of errors for every xilinx block.

 

Thank you so much for your help.

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Xilinx Employee
Xilinx Employee
2,727 Views
Registered: ‎08-01-2007

Re: Summary of frequent errors at design-modelling stage

I'm not aware of any documenation like this.

 

The main issue you will see is that user mismatch sizes or data types.  Or rate mismateches on multi-port blocks.

Chris
Video Design Hub | Embedded SW Support

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